Overview
Classification of analog-to-digital converters (ADCs).
Flash (Parallel Comparator) ADC
Flash ADCs, also called parallel-comparator ADCs, are a class of ADCs characterized by very high conversion speed. Many modern high-speed ADCs use this architecture and can reach sampling rates above 1 GSPS. A flash ADC uses multiple comparators to perform the conversion in a single comparison stage. Because the conversion rate is extremely high, an n-bit flash ADC requires 2^n - 1 comparators, resulting in a large circuit scale and higher cost. Flash ADCs are therefore used mainly in applications that demand very high speed, such as video ADCs.
The typical flash ADC consists of a resistor ladder, comparators, registers (D flip-flops), and an encoder. The resistor ladder is formed by n-1 resistors of value R in series and one resistor of value R/2. There are 2^n - 1 comparators, 2^n - 1 registers for sampling, and an encoder implemented with combinational logic to produce the digital output.
Flash ADCs offer very fast conversion and do not require a separate sample-and-hold circuit because the comparators and flip-flops perform sampling and holding. However, as the number of digital output bits increases, the encoder becomes more complex. For this reason, flash ADCs are typically used for outputs of no more than 4 bits in many practical designs.
Flash ADC resolution is limited by power and die area. Increasing resolution has little impact on conversion time, but it requires many precise resistor values and comparators, which increases analog design complexity. Each additional output bit roughly doubles the number of precision resistors and comparators required. Resolution is thus constrained by die size, input capacitance, power, and matching. Mismatches among the repeated parallel comparators can introduce static errors such as increased input offset. Flash ADCs can also produce discrete, non-monotonic outputs due to comparator metastability and encoder bubble errors, commonly referred to as "spark codes."
Successive Approximation Register (SAR) ADC
The successive approximation ADC (SAR ADC) is a widely used ADC type that converts an input analog signal to a digital output by iteratively approximating the input value.
SAR ADCs begin with the most significant bit (MSB) and determine each bit sequentially. A successive approximation register controls the conversion process. The SAR sets a trial digital code, which a digital-to-analog converter (DAC) converts to an analog voltage. The comparator compares the DAC output with the input voltage and yields a result that the SAR uses to decide the value of the current bit. This process repeats bit by bit until the least significant bit is resolved.
Operation steps:
- Apply the analog input to the SAR ADC comparator.
- The SAR sets the current trial bit to 1 or 0 according to the comparator output and adjusts the DAC output accordingly.
- The adjusted DAC output is compared with the input to decide the next bit.
- The approximation repeats until all bits are determined.
- The final digital code is the ADC output.
SAR ADCs converge by recursion, where each bit decision depends on prior results. They offer moderate conversion speed and can achieve high accuracy with relatively low power. The resolution depends on the number of SAR bits; more bits provide higher resolution. SAR ADCs are commonly used in low-to-medium resolution applications such as sensor measurements, audio sampling, and communication systems because they balance performance, complexity, and cost.
