Circuit function
This circuit uses planar N-channel and P-channel FETs in a complementary push-pull configuration to form a buffer amplifier. It shortens rise and fall times and is suitable for applications requiring wide bandwidth, fast switching, high input impedance, and low output impedance.
Operation
TT1 and TT2 are N-channel and P-channel FETs. Their VGB-to-ID characteristics must match; otherwise, an offset voltage will appear between the output and input. When this circuit is used inside an op amp feedback loop, the offset voltage becomes negligible.
The gate-source voltage of the planar FETs directly provides the bias between the base and emitter of the output stage. The base-to-base voltage required for the output stage is about 1.5 V, so FETs with equal drain saturation current IBSS should be selected and matched. TT3 is included to prevent variations in the FETs from changing the bias current of the output stage. For higher speed operation, increase the bias current so the output stage remains within its linear region.
Select output transistors according to collector current and allowable power dissipation. Choose devices with high FT and low COB.
Component selection
Although the circuit is ideal in principle, deviations in the VGB-to-ID characteristics of the input FETs (TT1, TT2) can shift the operating point. Therefore, choose FETs with appropriate drain saturation current and control their matching.
