Comparing HBM, HBM2, HBM3 and HBM3e
Technical overview of HBM memory: generations and HBM3E specs, market adoption in AI servers, supplier shares, and packaging technologies CoWoS and TSV for GPUs.
Memory & Storage Technology
Reconstructing RDMA Memory Disaggregation with CXL
Rcmp, a hybrid RDMA+CXL memory disaggregation system, uses CXL for intra-rack low-latency access and RDMA for cross-rack scalability with hot-page migration.
Via Stub Effects on DDR4 Parallel Links
Analysis of via stubs impact on DDR4-3200 signal integrity: simulations show max 73.1 mil stub for point-to-point channels; DIMM interconnect adds loss and deterministic jitter.
SK hynix Memory-Centric Computing System Overview
SK hynix's Hot Chips 35 overview of AiM compute-in-memory: architecture, workload mapping, scalability and software stack for large Transformer memory bottlenecks.
Inside Samsung's Memory Processing (PIM) Technology
Samsung's Hot Chips 2023 presentation details PIM and CXL-PNM approaches that offload GPT inference (GEMV-heavy) to HBM/LPDDR-PIM, reducing data movement, latency and energy.
Yangtze Memory Launches Ti600 Consumer NVMe SSD
Technical overview of Zhitai Ti600 SSD: PCIe 4.0 NVMe 2.0 interface, up to 7000 MB/s sequential read, M.2 2280 design, capacities 500 GB–2 TB.
SRAM Basic Circuits and Operating Principles
Technical overview of SRAM and DRAM fundamentals, comparing operating principles and detailing SRAM cell designs (D flip-flop, 4T and 6T), read/write/standby behavior.
NAND vs NOR Flash: Technical Comparison
Technical comparison of NAND Flash and NOR Flash covering memory cell structures, operating principles, market share, and selection guidance for embedded system design.
Types and Functions of Automotive Memory
Technical overview of the automotive memory market, use cases and module examples; discusses DRAM/LPDDR5, UFS/NOR storage, vendor positions and JEDEC standards.
Designing an EEPROM I2C Driver
Verilog I2C driver for 24LC64 EEPROM: read/write state machines, ACK handling, START/STOP timing, tri-state SDA control and simulation testbench with device model.
Structure Analysis of Stacked DRAM Storage Nodes
Technical summary of SNC via and SN capacitor formation in stacked DRAM, detailing SNC via structure, SN via cross-section, TiN electrodes, high?k dielectrics, and aspect?ratio reduction.
Will QLC All-Flash Replace Hybrid Storage?
Analysis of Gartner's 2023 enterprise storage trends focused on flash: QLC adoption, NVMe-oF deployment, and captive NVMe SSDs' impacts on architectures and procurement.
