Introduction
Multilayer HDI (High Density Interconnect) PCBs represent one of the most technically demanding product categories at AIVON. With microvias, blind and buried vias, tight tolerances, and complex stack-ups, these boards are widely used in smartphones, wearables, automotive electronics, 5G infrastructure, and high-speed computing devices where space and signal integrity are critical.
During PCB CAM review and engineering file processing, Multilayer HDI boards generate significantly more EQs than standard multilayer FR4 due to the precision required for laser drilling, plating, registration, and impedance control. Common issues include via spacing violations, via-in-pad treatment, stack-up mismatches, and impedance line adjustments.
This article consolidates the most frequent real-world EQs observed in Multilayer HDI production, drawn directly from CAM experience and order data, and provides clear design-side prevention strategies to help engineers reduce clarification cycles and improve first-pass yield.
Case 1: Microvia Spacing Rules in HDI Multilayer PCB Design
Case Overview
In high-density Multilayer HDI designs, microvias are frequently placed too close to each other or to adjacent traces to maximize routing density, especially in 6+ layer builds with multiple via levels.
Engineering Observation
During PCB CAM review, CAM software flags numerous locations where via-to-via or via-to-trace spacing falls below manufacturable limits for laser-drilled microvias.
Root Cause Analysis
Designers often apply standard via rules without fully considering HDI-specific constraints such as laser drilling accuracy, plating uniformity, and registration tolerances across multiple lamination cycles.
Design Impact
Insufficient spacing leads to plating defects, short circuits, compromised impedance control, reduced yield, and potential reliability failures under thermal or mechanical stress.
Recommended Solution
The spacing between vias is too small in your multilayer pcb design. Via-to-via spacing must be no less than 0.2mm and via-to-trace no less than 0.15mm. Please advise whether we should revise the file to maintain safe spacing.
These minimums account for laser-drill positional tolerance, copper plating thickness variation, and cumulative registration error across sequential laminations. Designs that push closer frequently show necking or voids in the via barrel after plating, especially in 6-layer and higher constructions with multiple microvia levels.
Engineering Takeaway
In Multilayer HDI designs, always maintain via-to-via spacing ≥ 0.2mm and via-to-trace spacing ≥ 0.15mm to ensure reliable plating and high yield.
| Feature Pair | Minimum Spacing | Primary Risk if Violated |
|---|---|---|
| Via-to-via | 0.2 mm | Plating shorts, barrel voids, reduced yield |
| Via-to-trace | 0.15 mm | Impedance deviation, potential short under thermal stress |
Case 2: Via-in-Pad Treatment for Multi-Layer HDI PCBs
Case Overview
BGA or fine-pitch areas in Multilayer HDI boards commonly feature vias placed directly in pads to save space and improve signal integrity.
Engineering Observation
Engineering review identifies vias-in-pad without explicit tenting or plugging strategy specified in the files.
Root Cause Analysis
Design files often omit detailed via treatment instructions while HDI processes require explicit handling to prevent solder wicking during assembly.
Design Impact
Without proper resin plugging, risks include solder voids, shorts during reflow, and reduced long-term reliability under thermal cycling.
During reflow the open via acts as a capillary path that draws solder away from the joint, creating voids or insufficient fillet volume. In fine-pitch BGA packages this can produce intermittent opens that only appear after thermal cycling or mechanical shock.
Recommended Solution
There are vias designed on pads. It is recommended to plug these vias with resin. Please confirm whether you accept resin plugging and any associated extra cost.
Engineering Takeaway
For vias-in-pad in Multilayer HDI designs, always specify resin plugging to ensure flat pads and reliable assembly performance.
| Treatment | Pad Flatness | Assembly Risk | Recommendation |
|---|---|---|---|
| No plugging / open via | Poor (solder wicking) | Voids, shorts, thermal-cycle opens | Not recommended |
| Resin plugging + planarization | Excellent | Minimal | Preferred for HDI |
Case 3: Resolving HDI PCB Multilayer Structure and Stackup Mismatches
Case Overview
Customers provide initial stack-up requirements for Multilayer HDI boards that may not perfectly align with available materials and press parameters.
Engineering Observation
Layer press confirmation shows differences between requested and proposed stack-up, particularly outer layer copper thickness and dielectric materials.
Root Cause Analysis
Material inventory and HDI lamination constraints often require minor adjustments to the ideal stack-up provided in the design files.
Available core and prepreg thicknesses, copper weights, and press-cycle limitations frequently force a practical compromise. Confirming the factory proposal early prevents impedance shifts that would otherwise require a respin after the first article.
Design Impact
Unconfirmed stack-up can cause impedance deviation, registration issues, or warpage in the final board.
Recommended Solution
Please kindly check whether the adjusted stack-up and impedance control is ok for you or not.
Engineering Takeaway
Review and approve the final factory stack-up early for all Multilayer HDI projects to avoid downstream impedance and registration problems.
Case 4: Impedance Control in Multilayer HDI PCB Design
Case Overview
High-speed signals in the multilayer circuit board require controlled impedance lines, but files often lack clear target values or proper reference layers.
Engineering Observation
DFM check reveals impedance lines without dedicated reference planes or shielding layers.
Root Cause Analysis
Designers sometimes assume automatic impedance control without providing target values or ensuring continuous reference layers across the HDI structure.
Design Impact
Uncontrolled or deviated impedance leads to signal integrity problems, board respins, and project delays.
Recommended Solution
Please advise whether we should do impedance control for the highlighted lines and provide target values (typical single-ended 50ohm, differential 90/100ohm). Adjustments to trace width/spacing may be needed.
Without explicit targets the fabricator cannot guarantee the correct dielectric height or copper geometry. Providing the values and accepting minor width/spacing tweaks allows the stack-up to be locked before laser drilling begins.
Engineering Takeaway
Always specify impedance targets and ensure dedicated, continuous reference layers for critical traces in Multilayer HDI designs.
Related Case: How to Avoid Common Solder Mask & Stackup Issues in 6-Layer HDI PCBs
Case 5: Confirming Via Types and Plating Requirements
Case Overview
Multilayer HDI PCBs may contain through-holes, blind vias, and buried vias with different electrical and mechanical functions. Clear plating specifications are essential to ensure that each hole is manufactured according to the intended design.
Engineering Observation
During CAM review, the drill drawing and Gerber data contained unclear or conflicting hole attributes at specific locations. The available manufacturing files did not clearly establish whether the indicated holes required copper plating.
Root Cause Analysis
In complex HDI designs, different hole types may serve different purposes, such as electrical interconnection, component mounting, or mechanical positioning. When plating attributes are missing or inconsistent across the drill files, fabrication notes, and other design data, the engineering team cannot reliably determine the intended manufacturing requirements from the available information alone.
Design Impact
An incorrect plating decision can affect electrical connectivity, hole dimensions, and the intended function of a hole. For example, a hole intended for electrical interconnection may fail to provide the required conductive path if plating is omitted. Conversely, unintended plating on a non-plated hole may affect electrical isolation or interfere with its mechanical function.
Recommended Solution
The plating requirements for the highlighted holes are unclear or inconsistent in the supplied manufacturing files. Please confirm whether these holes should be manufactured as plated through-holes (PTH) or non-plated through-holes (NPTH). If different hole types are required, please provide the corresponding drill attributes or updated fabrication notes so that we can finalize the manufacturing data accordingly.
Engineering Takeaway
Clearly define PTH and NPTH requirements in drill files and fabrication notes, and ensure that the hole attributes are consistent across all manufacturing documents. When the intended plating status cannot be determined confidently, obtain customer confirmation before releasing the final production data.
Related Case: How Conflicting Via Data and Soldermask Definitions Triggered CAM Review in a 4-Layer HDI PCB
Case 6: Half-Hole Geometry and HDI PCB Manufacturing Tolerances
Half-hole structures can be used in compact PCB designs where plated half holes are required for edge connections or mechanical integration. However, the half-hole geometry and spacing need to be clearly defined in the manufacturing documentation. During PCB CAM review, unclear half-hole requirements can create significant risks after compensation and manufacturing data preparation.
In this case, the original design showed a 1.3 mm-wide half-hole structure at the indicated location. However, the customer's purchase order did not specify whether the indicated holes should be manufactured as half holes. This created an engineering clarification requirement before production.
The original spacing between the half holes at the indicated location was approximately 0.2 mm. After applying the necessary manufacturing compensation, the remaining spacing would be less than 0.05 mm, which did not meet the minimum process capability of the production line.
Such a narrow gap can create manufacturing risks, including burrs around the hole wall and hole edge, rough copper surfaces, and insufficient separation between adjacent copper features. These issues may affect both manufacturing yield and the final appearance and reliability of the board.
To make the design manufacturable, the production data was adjusted by reducing the half-hole diameter by 0.1 mm and increasing the spacing to 0.5 mm. Before releasing the final manufacturing files, the customer was asked to confirm whether this adjusted half-hole structure was acceptable.
This case highlights an important consideration in half hole HDI PCB design: the nominal geometry shown in the original design does not always represent the final manufacturable geometry. Half-hole dimensions, spacing, plating requirements, and manufacturing compensation should be reviewed together during CAM and DFM engineering.
Key CAM Review Points
- Half-hole definition: Confirm whether the indicated holes are intended to be manufactured as plated half holes.
- Original spacing: Check the nominal spacing before applying manufacturing compensation.
- Compensation impact: Verify the remaining clearance after compensation rather than relying only on the original CAD dimensions.
- Minimum process capability: Ensure the final spacing meets the manufacturer's minimum production requirements.
- Edge and hole quality: Insufficient spacing can increase the risk of burrs, rough copper, and other edge-quality issues.
- Customer confirmation: When the production data requires a dimensional adjustment, obtain customer approval before final file release.
For complex half hole HDI PCB design, early clarification of the intended hole structure can prevent unnecessary engineering queries and reduce the risk of manufacturing deviations.
HDI Multilayer PCB Design Best Practices Before Fabrication
- Provide a complete and clearly labeled stack-up drawing with target impedance values.
- Maintain strict via spacing rules suitable for laser drilling.
- Specify via-in-pad treatment (resin plugging) early.
- Ensure continuous reference layers for all impedance-controlled traces.
- Clearly define plating attributes for all via types.
- Upload files early for a free DFM review.
- Refer to our Multilayer HDI Manufacturing Insights before finalizing complex designs.
Conclusion
Multilayer HDI PCBs offer outstanding density and performance but require meticulous attention to via structures, stack-up, and impedance during design. By addressing the common EQs outlined above, engineers can achieve smoother production, higher yields, and faster time-to-market.
FAQs
Q1: What is the recommended via spacing for multilayer HDI PCBs?
A1: The appropriate via spacing depends on the via diameter, pad size, copper features, layer structure, and manufacturing process. Designers should follow the fabricator's design rules and review critical spacing during DFM to identify potential manufacturing risks before production.
Q2: Should vias-in-pad be resin plugged in HDI designs?
A2: Resin plugging and planarization are commonly used for vias-in-pad in fine-pitch applications, particularly in BGA layouts, where a flat pad surface is important for reliable soldering. The appropriate via treatment depends on the component footprint, via structure, and assembly requirements. Confirm the required finish with your PCB manufacturer before fabrication.
Q3: When should the stack-up be confirmed for an HDI PCB?
A3: The stack-up should be reviewed early in the design process, ideally before routing is finalized. Layer arrangement, dielectric thickness, copper thickness, material selection, and microvia structures can all affect impedance control and manufacturability. Early coordination with the manufacturer helps identify potential design constraints and reduce engineering changes later.
Q4: Why is impedance control challenging in multilayer HDI PCB designs?
A4: Impedance control in HDI PCBs depends on trace geometry, dielectric properties, copper thickness, reference-plane continuity, and the overall stack-up. Designers should specify target impedance values and identify the relevant signal layers in the fabrication documentation. The manufacturer can then evaluate the design and recommend suitable adjustments during CAM and DFM review.
Q5: Can multilayer HDI PCBs support different copper thicknesses?
A5: Yes. Copper thickness can be selected according to current requirements, signal integrity, thermal performance, and the overall layer structure. However, the available options depend on the PCB manufacturer's process capabilities and the specific design. Confirm copper thickness requirements during stack-up review to ensure that electrical performance and manufacturing constraints are addressed together.
