Introduction
This 14-layer, 2.0mm thick TG170 FR-4 board presented several significant manufacturability challenges during our CAM engineering review. Designed for a power-related application with controlled impedance requirements, the board featured a mix of standard through holes, non-plated holes, resin-plugged vias, and tight copper features near the outline.
Multilayer boards with 14 layers and mixed copper weights (2oz outer, 1oz inner) are inherently complex. They often require careful stackup optimization, precise impedance modeling, and clear clarification on plugging and solder mask strategies. During our standard DFM review, our CAM team identified multiple areas where the design intent conflicted with reliable production capabilities.
In this case study, we document the key engineering questions raised, the risks involved, and how our team resolved them before releasing the job for production. These types of issues are exactly why experienced PCB manufacturers perform thorough CAM review rather than proceeding directly to fabrication.
Order Overview
The project involved a 244mm × 267mm 14-layer PCB built on FR-4 TG170 material with a finished board thickness of 2.0mm (#FR4-20260515-068). Outer layers used 2oz copper while inner layers were 1oz. The board required ENIG surface finish, 100% flying probe electrical testing, and resin plugging for selected vias. Panelization was specified as 1×1 with no V-CUT.
Key manufacturing features included controlled impedance routing, multiple non-plated holes, and specific solder mask requirements. The customer requested an 18-day delivery for 10 pieces. While the base specifications were standard for high-reliability applications, the Gerber data contained several areas requiring clarification before we could safely proceed with production tooling.
Main Engineering Questions Found During CAM Review
File & Manufacturing Data Issues
Our CAM engineer immediately noticed inconsistencies between the provided fabrication notes and the actual Gerber/Drill data. Several impedance lines referenced in the stackup documentation could not be clearly identified in the design files. After reviewing the stackup, we found that the proposed line widths would not achieve the target impedance values using our standard TG170 material and dielectric thicknesses.
Figure 1: Recommended impedance lines referenced in the stackup documentation
We noticed the blind via spacing was below the safe manufacturing tolerance in some areas, so our engineering team recommended modifying the production data. If ignored, this could have led to drill breakout, unreliable plating, and potential via cracking during thermal cycling, resulting in field failures and significant yield loss.
Solder Mask & Pad Definition Issues
One of the most critical issues involved solder mask openings. On the top layer, multiple SMD pads had solder mask windows of only 3.94 mil — significantly below our reliable minimum of 9 mil for consistent ENIG processing. We also found several large 128 mil holes where the solder mask opening was smaller than the hole itself.
Figure 2: Only 3.94 mil solder mask windows on SMD pads
Figure 3: Large 128 mil holes on SMD pads
Our engineer suggested adjusting these openings because we noticed that undersized solder mask apertures increase the risk of solder mask encroachment on pads, leading to poor solderability and assembly defects. If production had continued without adjustment, we would likely have seen exposed copper edges, solder bridging risks, and cosmetic defects that fail IPC-A-600 Class 2 acceptance criteria.
Resin Plugging Clarification
The customer specified resin plugging, but the data created ambiguity. Some vias had double-sided solder mask openings while others appeared as test points. Our team could not confidently determine which specific holes required plugging versus which needed open mask for testing or assembly.
Figure 4: Vias on double-sided solder mask openings while others on test points
Figure 5: Guard vias on pads
We raised this as a formal engineering question because incorrect plugging decisions can cause serious reliability problems. If non-plugged vias were filled or vice versa, it could lead to resin voids, trapped air, or incomplete filling, resulting in delamination or intermittent connections under thermal stress.
Copper Clearance to Outline & Routing Concerns
On Layer 3 and several outer layers, copper features were positioned too close to the board outline. In some cases, copper was tangent to the routing path. We noticed the copper clearance near the outline was insufficient, so our CAM team identified potential exposed copper after routing.
Figure 6: Copper features were positioned too close to the board outline.
Figure 7: Potential exposed copper after routing
If this had not been addressed, the routing process could cause copper burrs, peeling, or copper rolling at the edges. This is particularly problematic on 2oz outer layers and would likely result in edge shorting risks during assembly or conformal coating application. According to typical IPC-2221 guidelines for edge spacing, these features approached manufacturability limits.
Hole & Tolerance Issues
Several non-plated holes had overly tight tolerance requirements that would be difficult to control consistently in production. Additionally, some non-plated holes were positioned directly on SMD pads. Our team decided to use a second drill operation to preserve adequate pad size while maintaining the non-plated requirement.
Figure 8: Non-plated holes were positioned directly on SMD pads.
We also found multiple instances where component pads were smaller than their respective holes, which violates standard DFM rules and risks hole breakout during drilling.
Manufacturing Risks and DFM Insights
This case highlighted several recurring DFM challenges in high-layer-count designs. Customers often underestimate the impact of solder mask opening sizes on ENIG plating quality and the importance of clear via plugging callouts. The combination of tight impedance requirements with aggressive copper-to-edge clearances created multiple conflict points.
If left unaddressed, these issues could have caused production delays of several days, increased scrap rates, and potential field reliability problems. The most serious risk was inconsistent resin plugging combined with marginal solder mask definition, which could lead to via failures under power cycling.
How the Engineering Team Resolved the Issues
Our engineering team prepared updated production files incorporating the necessary adjustments. For impedance control, we provided a revised stackup drawing and adjusted line widths accordingly. Solder mask openings were expanded to manufacturable sizes while preserving pad integrity.
For the resin plugging, we requested customer confirmation on specific hole lists and clearly marked them in our working files. Copper features near the outline were reviewed and adjusted where necessary to maintain minimum clearance. Our CAM engineer confirmed that the solder mask layers conflicted with the fabrication notes in several locations, so we aligned them with standard production capabilities.
All changes were documented and sent back to the customer for final approval before proceeding.
Final Manufacturing Outcome
After receiving customer confirmation on the key points, we finalized the production data. The stackup was optimized for both impedance and material availability. All critical DFM issues were resolved, and the job was released for tooling and production with improved manufacturability and reduced risk.
Key Takeaways for PCB Designers
- Always verify solder mask openings against your manufacturer’s minimum capabilities — especially for ENIG processes.
- Provide clear, unambiguous via plugging specifications with reference drawings when using resin fill.
- Maintain adequate copper-to-edge clearance (typically 0.3-0.5mm depending on copper weight) to prevent routing defects.
- Ensure impedance requirements include complete trace identification and realistic target values for the chosen material.
- Use consistent layer naming and include detailed fabrication notes that match your Gerber data.
- Consider second-drill operations for non-plated holes overlapping SMD pads during initial design.
FAQ
Q1: Why are small solder mask openings problematic for ENIG surface finish?
A1: Openings below 9 mil often lead to incomplete plating coverage, solder mask residue on pads, and poor wetting during assembly. This increases defect rates and can cause open solder joints.
Q2: What risks occur when copper is too close to the board outline?
A2: Routing can cause copper burrs, peeling, or exposed edges. This leads to potential short circuits at the board perimeter and cosmetic failures during final inspection.
Q3: Why is clear specification important for resin plugged vias?
A3: Without clear callouts, manufacturers cannot determine which holes need plugging versus those requiring open mask for probing or assembly. Incorrect plugging can cause voids, pressure issues during lamination, or reliability failures.
Q4: How does CAM review prevent production problems in multilayer PCBs?
A4: It identifies conflicts between design intent and manufacturing capability before drilling and plating. This prevents scrap, reduces engineering change orders after production starts, and improves overall yield.
Q5: Can tight impedance requirements be met without adjusting trace widths?
A5: Often not, especially when the stackup and material dielectric constants differ from the designer's modeling tool. Manufacturers typically adjust widths based on actual production parameters to achieve target impedance within tolerance.
