This engineering case examines a recent 18-layer high-density PCB order (#FR4-20260313-033) that presented multiple manufacturability challenges during our standard CAM review process. The board measures 163 × 102 mm, uses TG170 FR-4 material at 2.0 mm finished thickness, and incorporates 0.5 oz / 1 oz copper with ENIG surface finish. While the design appeared solid on paper, detailed DFM analysis revealed several critical conflicts between the customer's intended electrical performance and actual production capabilities.
As a senior CAM engineer with over 15 years in multilayer fabrication, I’ve seen how subtle stackup and reference layer decisions can dramatically impact impedance control and overall yield. In this case, our engineering team raised several targeted EQs (Engineering Questions) to the customer before releasing the job to production. These clarifications prevented potential major issues in impedance performance, plating consistency, and mechanical reliability.
Order Overview
This was a 18-layer rigid PCB built on standard FR-4 TG170 material with a finished board thickness of 2.0 mm. Outer layer base copper was specified as 0.5 oz, with inner layers at 1 oz. The design featured a minimum hole size of 0.1 mm, 100% flying probe testing, and ENIG surface finish. Panelization was customer self-panelized (1×1), with mechanical routing and tree resin hole plugging specified.
The board included impedance requirements, with specific trace widths called out for 55 ohm control on outer layers. Press-fit holes were noted in fabrication instructions but lacked critical dimensional details. Quantity was small (5 pcs), with a 50-day lead time, which allowed our team sufficient time for thorough DFM review and iterative clarification with the customer.
Main Engineering Questions Found During CAM Review
1. Impedance Control Challenges: Reference Layer Shielding and Copper Thickness Conflicts
The most significant issues centered around impedance control. The customer specified certain outer layer traces (11.5 mil) referencing L3 for 55 ohm control. However, after loading the full ODB++ data into our CAM system, our engineer noticed that many of these traces on L2 were already shielded by copper on L3, making the reference invalid for the intended calculation.
Figure 1: SP1-S Stackup
We also identified similar shielding problems on L4/L5 pairs and single-ended 5 mil traces on L2 and L17 that were partially covered by IC pads. Our CAM team identified that even after adjusting to minimum 3 mil traces with dual-layer reference, the achievable impedance only reached approximately 47 ohms.
Figure 2: Shielding problems on L4/L5 pairs
Figure 3: Sheet data about single-ended 5 mil traces on L2 and L17
Additionally, the customer requested finished outer copper at 1 oz, but with our standard hole plating requirement of ≥30 μm, the final plated copper would exceed 1.5 oz. This directly impacted impedance calculations across multiple layers. We noticed these discrepancies early in the stackup verification phase.
Figure 4: Base copper thickness
If these issues had been ignored, the finished boards would likely have delivered impedance values significantly outside the target range, leading to signal integrity problems, potential timing issues in high-speed circuits, and possible field failures. In extreme cases, this could result in complete board respin costs for the customer.
2. Press-Fit Hole Specification Ambiguity
The fabrication notes mentioned press-fit holes, but no specific drill size or tolerance was provided in either the drill drawing or separate documentation. Our team could not locate corresponding details in the panelization files either.
Figure 5: Press-fit hole without specific drill size
Press-fit holes require precise diameter control to ensure proper mechanical interference without damaging the plating or causing delamination during insertion. Without clear specifications, we had to pause and request confirmation to avoid producing holes that were either too loose (poor retention) or too tight (risk of barrel cracking or pad damage).
Had production proceeded without clarification, we risked inconsistent insertion force, potential via cracking under press-fit stress, or long-term reliability failures in the field.
3. Stackup Copper Thickness and Plating Inconsistencies
In the provided stackup, L11 was called out for H oz base copper plus plating. However, this layer had no blind vias, meaning no additional plating was required. Our engineer suggested removing the unnecessary plating callout to maintain consistent copper thickness and avoid over-plating that could affect etching uniformity and impedance on adjacent layers.
Figure 6: L11 was called out for H oz base copper plus plating.
We also adjusted the overall stackup slightly and modified some impedance trace widths to better align with achievable manufacturing parameters while staying as close as possible to the original design intent.
4. Material Specification Conflicts
The customer requested a thermal conductivity of 1.0 W/m·K, which is significantly higher than standard FR-4 (typically 0.2–0.3 W/m·K). We had to confirm this requirement, as achieving higher thermal performance usually requires special high-Tg or filled materials that would impact cost, availability, and the overall stackup dielectric properties.
Manufacturing Risks and DFM Insights
This case highlights several recurring DFM pain points in complex multilayer designs. Impedance-related EQs are among the most common we encounter on 12+ layer boards because designers often calculate impedance based on ideal reference planes without accounting for actual copper pour patterns that create shielding.
If left unaddressed, such mismatches frequently lead to boards that pass flying probe testing but fail in functional system testing due to signal reflections or timing violations. The copper thickness conflict with plating is another classic issue — designers specify base copper without considering the final plated thickness required for reliable via barrel strength (especially important with 0.1 mm holes and 2.0 mm thickness).
From a manufacturing perspective, proceeding without these clarifications could have resulted in board warpage from uneven copper distribution, via cracking under thermal stress, or poor solderability due to excessive copper on pads. In our experience, these types of issues contribute significantly to yield loss in small-batch high-layer-count runs.
How the Engineering Team Resolved the Issues
Our engineering team worked closely with the customer through multiple rounds of clarification. For the impedance issues, we provided detailed cross-section simulations and proposed adjusted trace widths and stackup dielectric values. The customer approved our micro-adjustments to L2/L17 traces and reference configurations.
We confirmed standard press-fit hole parameters based on common industry sizes suitable for the board thickness and provided the customer with our recommended tolerances aligned with IPC-6012 Class 2 requirements. The thermal conductivity requirement was clarified as a target rather than strict material spec, allowing us to proceed with standard TG170 FR-4 while noting the realistic performance.
Solder mask was standardized to our reliable red ink with customer approval, and marking layers were completed based on the partial BO layer information provided. All changes were documented and re-verified in our CAM system before final production release.
Final Manufacturing Outcome
After receiving customer confirmation on all EQ points, the production data was updated, stackup optimized, and the job successfully released to the factory floor. The 5-piece prototype run proceeded without further issues, with full electrical testing completed as specified.
Key Takeaways for PCB Designers
- Always verify actual reference planes in your layout tool against final copper pour patterns — shielding effects are common on dense inner layers.
- Specify finished copper weight clearly and understand how plating will affect final thickness, especially for boards requiring ≥30 μm hole copper.
- Provide complete mechanical hole specifications, including tolerances for any press-fit or special diameter requirements.
- Include full impedance calculation documentation with reference layers, target values, and tolerance ranges in fabrication notes.
- Cross-check material properties (thermal conductivity, Tg, Dk/Df) against standard FR-4 capabilities before finalizing the BOM.
- Ensure all special markings (Date, Lot, S/N) have complete layer definitions across relevant sides.
- Consider providing both Gerber and ODB++ data for complex multilayer jobs to facilitate accurate CAM review.
FAQ
Q: Why is reference layer shielding such a common issue in multilayer impedance control?
A: In dense designs, copper fills and ground planes on adjacent layers often overlap traces in ways not obvious during initial stackup calculation. This changes the effective dielectric environment and coupling, leading to impedance deviations that only become apparent during professional CAM analysis.
Q: What happens if press-fit hole dimensions are not clearly specified?
A: Without precise diameters and tolerances, manufacturers must guess standard values. This risks either insufficient retention force or excessive stress causing plating cracks, pad lifting, or delamination during connector insertion.
Q: How does final plated copper thickness affect impedance?
A: Thicker final copper increases trace height and width after etching, lowering impedance compared to calculations based on base copper alone. This is especially critical on outer layers where plating adds substantial thickness.
Q: Can standard FR-4 meet high thermal conductivity requirements?
A: Standard FR-4 typically offers 0.2–0.3 W/m·K. Achieving 1.0 W/m·K generally requires thermally enhanced materials with ceramic fillers, which change Dk values and require full stackup revalidation.
Q: Why do CAM engineers sometimes adjust trace widths during DFM review?
A: Adjustments ensure the design stays within reliable etching and plating capabilities while achieving the closest possible impedance match. These changes are always submitted for customer approval before implementation.
Q: What is the risk of inconsistent fabrication notes across layers?
A: Inconsistent notes can lead to misinterpretation of requirements (such as different copper weights per layer or conflicting surface finish instructions), resulting in production errors, delays, or boards that do not meet electrical performance targets.
