In late March 2026, we handled a 2-layer FR-4 order with mixed 1oz/2oz copper, 1.0mm thickness, and customer-provided panelization. While 2-layer boards are generally straightforward, this case presented several practical DFM challenges involving via treatment, panel size consistency, and fabrication marking placement. Multiple engineering questions (EQs) were necessary to align the customer's intent with manufacturable production data.
This real-world engineering review demonstrates how even simple double-sided boards can encounter issues that, if left unaddressed, risk defects in via reliability, dimensional accuracy, and assembly quality. As a senior CAM engineer, I always emphasize that early clarification prevents downstream problems.
Order Overview
This was a 2-layer FR-4 TG170 PCB ( #FR4-20260428-012 ) project with dimensions 286 × 141mm, 1.0mm finished thickness, and 20pcs quantity (5 sets). Copper weights were 1oz on one side and 2oz on the other. The board featured green solder mask and white silkscreen on both sides, ENIG surface finish, 0.3mm minimum hole size, 100% flying probe testing, V-cut depanelization in 1x4 format, and aluminum via plugging for selected holes.
The customer supplied their own panelization file and specific fabrication notes for via plugging and UL/date code markings. During CAM review, discrepancies between the provided files, dimensions, and marking requirements became evident, requiring detailed clarification.
Main Engineering Questions Found During CAM Review
1. Selective Via Plugging Requirements (Copper Paste vs Cover)
The customer specified that certain vias shown in attached images should receive copper paste plugging, while all other vias should use standard cover plugging. We noticed this selective requirement during data analysis and raised an EQ for confirmation on exact via locations and final expectations after surface finish.
Figure 1: vias shown in attached images should receive copper paste plugging
Our engineer suggested verifying the via list because inconsistent plugging treatment on a 2-layer board with 2oz copper can affect flatness and solderability. Copper paste plugging provides better thermal and electrical performance for high-current paths, but requires precise execution to avoid pad recession or incomplete filling.
If ignored, mismatched via treatment could lead to uneven surfaces, poor component seating, or via cracking under thermal stress. In production, this often results in assembly failures or reduced reliability, particularly when boards undergo reflow. We confirmed the specific vias for paste plugging to maintain consistency with the customer's design intent.
2. Panel Dimension and Process Edge Discrepancy
A notable issue was the panel size mismatch. The customer's processing notes indicated 141×286mm, but the supplied panel file included process edges, resulting in actual dimensions of 141×288mm. We flagged this immediately and asked which dimension should take precedence for V-cut and routing.
Figure 2: customer's processing notes indicated 141×286mm
We noticed that the added process edges affected V-cut positioning and overall panelization stability. Accurate panel dimensions are critical for mechanical forming and depanelization quality. Proceeding with the wrong size risked incorrect V-cut placement, leading to board edge damage or dimensional inaccuracy in the final shipped boards.
According to standard manufacturing tolerances, such discrepancies can cause fit issues in downstream assembly. Our team recommended confirming the final panel size based on the file with process edges to ensure proper V-cut spacing of 2.0mm where applicable.
3. Silkscreen Marking Placement and Overlap Issues
The customer required Date Code, UL marking, and factory code inside a specific box on the top layer silkscreen, referencing a PDF document. However, no exact position or content details were provided. Additionally, some characters overlapped component pads with no room to move.
Figure 3: customer requests that the factory code and UL be added on the top layer silkscreen
Figure 4: some characters overlapped component pads with no room to move
Our CAM engineer identified that placing markings near existing silkscreen elements risked readability issues and potential solder mask conflicts. We also noted the instruction not to add cycle marks near the top layer markings due to bottom layer constraints.
If left unconfirmed, silkscreen on pads could cause poor solderability and cosmetic defects. Unclear marking placement might result in missing or misplaced UL/date codes, leading to compliance problems. We worked with the customer to finalize positions that avoided critical areas while meeting all marking requirements.
Manufacturing Risks and DFM Insights
This 2-layer case highlighted recurring challenges in customer-provided panelization and special process instructions:
- Inconsistent via plugging specifications on mixed copper weight boards can affect thermal performance and assembly yield.
- Panel dimension conflicts between notes and actual files frequently cause V-cut misalignment.
- Ambiguous marking requirements combined with silkscreen overlap often require multiple revision cycles.
Without proper EQ clarification, risks included exposed copper after V-cut, incomplete via fill leading to open circuits, misplaced regulatory markings, and pad contamination from overlapping legend. In similar past orders, unaddressed panel size issues resulted in scrap due to incorrect final board dimensions.
How the Engineering Team Resolved the Issues
We provided annotated screenshots clearly marking the vias for copper paste plugging and requested final panel size confirmation. For markings, we suggested optimal positions within the customer's specified box while avoiding pad overlap. Our team adjusted the working files accordingly after receiving customer approvals.
The panelization was standardized to the file dimensions with process edges, and selective via plugging was implemented as confirmed. This collaborative process ensured all special requirements were met without compromising manufacturability.
Final Manufacturing Outcome
After several rounds of clarification on via plugging, panel dimensions, and marking placement, all engineering questions were resolved. The updated working files were approved, and the job was successfully released for production with optimized parameters.
Key Takeaways for PCB Designers
- Clearly specify selective via plugging requirements with reference images or drill lists to avoid ambiguity.
- Ensure panelization files match processing notes for overall dimensions and V-cut positions.
- Provide detailed marking instructions including exact content, layer, and position to reduce back-and-forth communication.
- Avoid placing silkscreen legend on component pads; maintain adequate clearance for solderability.
- When using mixed copper weights on 2-layer boards, verify via treatment compatibility with thermal and electrical needs.
- Include process edge considerations in panel drawings when submitting self-panelized designs.
- Reference previous similar orders or UL file numbers to accelerate marking confirmation.
FAQ
Q1: Why is selective copper paste via plugging important?
A1: Copper paste provides superior conductivity and thermal dissipation for high-current vias compared to standard mask plugging, but must be clearly specified to ensure correct application and flat pad surfaces.
Q2: What problems arise from panel dimension mismatches?
A2: Discrepancies between notes and files can cause incorrect V-cut placement, leading to board edge damage, dimensional errors, or scrap after depanelization.
Q3: Why do factories request exact positions for UL and date code markings?
A3: Without clear location details, markings may overlap pads, become unreadable, or conflict with other silkscreen elements, affecting compliance and aesthetics.
Q4: Can silkscreen legend be placed on component pads?
A4: It is strongly discouraged as it interferes with solder paste application and reflow, commonly causing assembly defects like weak joints or tombstoning.
Q5: How should designers handle process edges in self-panelized files?
A5: Clearly communicate final board size versus panel size including edges, and confirm V-cut or routing margins to prevent manufacturing tolerance issues.
