In late March 2026, we processed a compact 6-layer HDI PCB order with blind vias, tight 32×46mm form factor, and mixed copper weights. Although small in size, this high-density design triggered multiple critical engineering questions during CAM review, primarily around stackup compatibility, solder mask capability on fine-pitch SMD pads, and via placement in BGA areas.
As a senior CAM engineer with over 15 years of experience, I've seen many compact HDI boards face manufacturability gaps between designer intent and production reality. This case demonstrates why thorough DFM review is essential before releasing HDI jobs for production.
Order Overview
This was a 6-layer FR-4 TG150 HDI PCB ( #FR4-20260418-085 ) (2-stage blind vias) measuring 32 × 46mm with 1.0mm finished thickness and 15pcs quantity. Outer layers used 1oz copper, inner layers 0.5oz. The board featured green solder mask and white silkscreen on both sides, ENIG surface finish, 0.1mm minimum hole size, 100% flying probe testing, and V-scoring depanelization in 3×1 format. The customer specifically noted that the new Gerber data required a custom stackup (JP06101H-3313A2).
During initial data review, several mismatches between the provided Gerber files, stackup requirements, and our standard HDI processes required detailed clarification.
Main Engineering Questions Found During CAM Review
1. Stackup and Material Confirmation
The customer requested a specific stackup (JP06101H-3313A2). After reviewing the files, our team identified that the customer's design used Shengyi TG150 material, which is not our regular stock. We proposed our standard equivalent and requested confirmation of the exact press stackup.
Figure 1: FR4 TG150 stackup
We noticed discrepancies in the inner layer copper distribution, particularly on L4 which had very low copper density with only traces and isolated pads. After reviewing the stackup, we found this could cause resin starvation during lamination.
Figure 2: low copper density areas vs copper pour design
If ignored, low copper density areas risk delamination or board warpage, especially in thin 1.0mm HDI constructions. Our engineer recommended allowing removal of non-functional isolated pads on inner layers to improve resin flow and yield, a common practice in HDI manufacturing.
2. Solder Mask Bridge on Fine-Pitch SMD Pads
Multiple areas showed SMD pad spacing below our minimum 5.9mil solder mask bridge capability. Some gaps were as tight as 3.15mil. We raised an EQ highlighting these locations and explained our process limitations.
Figure 3: SMD pad spacing below our minimum 5.9mil solder mask bridge capability
In high-density HDI designs, insufficient spacing often leads to solder mask bridging failure or no bridge at all. If production continued without adjustment, it could cause solder shorts during assembly or poor insulation between pads. We suggested the customer review and potentially increase spacing or accept mask clearance in critical areas.
3. 0.1mm Vias in BGA Area and Via Treatment
Several 0.1mm vias were placed directly in BGA pads. We noted that such small holes are difficult to drill reliably and would reduce the effective soldering area. Additionally, some BOT vias had isolated solder mask openings.
Figure 4: 0.1mm vias were placed directly in BGA pads
Our CAM engineer recommended increasing the drill size to 0.2mm where possible to improve plating reliability and avoid quality risks. We also sought confirmation on whether the isolated via openings required special treatment. Proceeding with 0.1mm vias in BGA pads risked drill breakage, incomplete plating, or assembly defects.
4. Panelization and General Process Parameters
The customer's 1×3 panelization created excessive waste. We proposed an optimized 3×2 layout and requested confirmation. We also provided our standard process parameters (ENIG thickness, warp control, hole tolerances, etc.) for customer approval.
Manufacturing Risks and DFM Insights
This compact 6-layer HDI case highlighted several recurring issues in high-density designs:
- Stackup documentation that does not align with factory material availability often delays production.
- Extremely tight SMD spacing below solder mask bridge capability is a frequent cause of EQs in HDI boards.
- Placing micro-vias (0.1mm) directly under BGA pads significantly impacts assembly yield.
- Low copper density on inner layers can cause lamination defects in thin boards.
Had these issues been ignored, risks included solder mask shorts, via cracking, delamination due to resin starvation, reduced BGA solder joint reliability, and overall low production yield. In similar HDI jobs, unaddressed solder mask bridge issues led to assembly failures and customer returns.
How the Engineering Team Resolved the Issues
We sent detailed annotated screenshots for each problem area. The customer confirmed the stackup with our recommended adjustments, accepted removal of non-functional inner layer pads, and agreed to the optimized panelization layout. For the BGA vias, we received approval to enlarge drill sizes where feasible.
Our engineering team updated the working files with confirmed process parameters and re-verified solder mask bridge areas. This collaborative approach significantly reduced manufacturing risk.
Final Manufacturing Outcome
After multiple rounds of EQ clarification on stackup, solder mask, vias, and panelization, all issues were resolved. The updated production data was approved and the job was released for manufacturing.
Key Takeaways for PCB Designers
- Provide complete and accurate stackup drawings early, including material specifications.
- Respect minimum solder mask bridge requirements (typically 5.9mil+) when designing fine-pitch SMD layouts.
- Avoid placing micro-vias (0.1mm) directly under BGA pads whenever possible.
- Ensure adequate copper density on all inner layers to prevent lamination issues.
- Consider panelization efficiency — factory optimization can reduce material waste significantly.
- Clearly define blind via requirements and confirm drill sizes for HDI designs.
- Review Gerber data for isolated via openings and non-functional pads before submission.
FAQ
Q1: Why is low inner layer copper density problematic in HDI PCBs?
A1: It can cause resin starvation during press, leading to delamination, voids, or warpage, especially in thin boards.
Q2: What happens when SMD pad spacing is too tight for solder mask?
A2: Solder mask bridges may fail, causing shorts during assembly or insufficient insulation between pads.
Q3: Why should designers avoid 0.1mm vias in BGA pads?
A3: Small holes reduce soldering area, are harder to plate reliably, and increase drill-related defects.
Q4: How important is panelization optimization for small boards?
A4: Poor panelization leads to excessive material waste and higher costs. Factory-recommended layouts often improve efficiency significantly.
Q: Why do factories request confirmation on non-functional pads?
A: Removing them improves lamination quality and yield without affecting electrical performance.
