Congestion Control in Ethernet Storage Networks
Guide to detecting and diagnosing microbursts and PFC storm congestion in lossless Ethernet storage networks, covering Nexus 9000 telemetry, UDP/IO flow monitoring, and TxWait
Guide to detecting and diagnosing microbursts and PFC storm congestion in lossless Ethernet storage networks, covering Nexus 9000 telemetry, UDP/IO flow monitoring, and TxWait
Sony scales production of laser diodes with Seagate to enable 30TB 3.5-inch HDDs, boosting areal density and cutting power use for AI data center storage.
Overview of the memory hierarchy - registers, cache, DRAM, disk - covering benefits (speed/capacity tradeoffs, caching, cost, reliability), virtual memory, and memory striping
Explains registers as the fastest CPU memory and outlines the memory hierarchy: registers, cache, main memory, and secondary storage, with performance and capacity trade-offs.
Technical overview of using EEPROM data flash for vehicle counting and uptime logging: EEPROM write strategy, storage capacity, initialization, and implementation notes.
Technical overview of FeRAM (ferroelectric RAM): operation with PZT capacitors, comparisons to flash and EEPROM on speed, endurance, and power.
TSMC and ITRI MRAM developments: technical comparison of STT-MRAM and SOT-MRAM, device performance (~10 ns), power, scalability and use in in-memory computing and caches.
GALAX Star Yao 7000 Plus PCIe 4.0 SSD review: 1TB Phison PS5027-E27T drive that exceeds rated 7000/6000 MB/s, SLC cache sizing and real-world game/file tests.
S7-1200 memory card guide: functions, Program vs Transfer card modes, STEP 7 Basic procedures for inserting, uploading/downloading projects, firmware updates and password reset.
Technical overview of Ambarella CV3 CVflow architecture and tools—partial buffers, parallel streaming, operator acceleration, sparsity and quantization—to mitigate the memory wall.
Survey of data storage technologies—magnetic, optical and semiconductor—analyzing capabilities, applications and evolution, highlighting NAND flash and HBM trends.
Technical overview of FRAM endurance: fatigue mechanisms, process-node performance (0.13 μm), device/material observations and signal-margin behavior up to 10^15 cycles.