Copper sitting too close to the outline is one of the most frequent CAM flags on FR4 boards. The CAD file shows a clean 0.2 mm gap. After routing, that gap is gone. The edge is bright copper, the plane is exposed on the routed wall, or a trace has been nicked. FR4 PCB edge clearance is not a cosmetic rule. It is the allowance that keeps copper inside the finished board after mechanical tolerance is consumed.
The number that matters is not the distance drawn to the outline line. It is the remaining distance after the router, V-score, or punch has done its work.
What Copper-to-Edge Distance Actually Measures
Copper-to-edge is the shortest distance from any copper feature—trace, plane, pad, or via annular ring—to the finished board outline. Finished outline. Not the Gerber outline path.
Outer-layer copper and inner-layer copper are not the same problem. Outer copper that reaches the edge becomes exposed metal on the board perimeter. Inner copper that reaches the edge becomes a sliver of metal on the routed sidewall. Both fail electrical isolation and both fail most coating processes.
Planes are worse than traces. A plane pour that follows the outline at 0.15 mm looks tidy in the layout tool. After routing it is a continuous copper band around the board. That is the feature most shops reject first.
Why Routing Tolerance Eats the Clearance Drawn in CAD
A typical CNC route on 1.6 mm FR4 holds roughly ±0.10 to ±0.15 mm to the programmed path. Tool wear, fixture shift, and panel position add more. V-score is less precise on the remaining web. Punch tools add their own die clearance.
If copper is placed 0.25 mm from the CAD outline and the cutter walks 0.12 mm toward the copper, the remaining dielectric is 0.13 mm. That is already inside most shops' "exposed copper" reject threshold. Walk the other way and the board is undersize, which is a different reject.
The clearance in the design file must absorb:
- routing positional tolerance
- cutter radius and path compensation
- outline layer-to-layer registration on inner copper
- any secondary process that touches the edge (bevel, plating, scoring)
Designers who set copper-to-edge equal to the fabricator's published minimum are using the minimum as a target. That number is the floor after process variation, not the drawing dimension.
Exposed Copper, Edge Shorts, and Isolation Failures
Exposed copper on the perimeter does three things that do not show up in a netlist check.
It creates a conductive path to whatever the board touches—chassis, enclosure rib, operator finger, adjacent board in a rack. It oxidizes and can grow contamination under humidity. It also breaks solder-mask and conformal-coat coverage at the edge, so the copper stays bare for the life of the product.
Inner-layer exposure is quieter and more dangerous. The routed wall cuts through the laminate and shears the inner copper. You get a thin metal line on the dielectric edge. That line is electrically connected to a plane. On a high-voltage or safety-isolated design it is an isolation failure. On a dense digital board it is a latent short waiting for conductive dust or condensation.
Gold-plated edges and castellation are intentional exceptions. They are specified, plated, and inspected as features. Accidental edge copper is not.
Board-Edge Stress and Copper Lift During Depanel
FR4 at the outline is already the weakest mechanical zone. Routing leaves a rough glass-resin edge. V-score leaves a notch. Breakaway tabs concentrate bending stress in a few millimeters of laminate.
Copper that runs to that edge becomes a peel-initiation site. During depanel the laminate flexes. The copper-to-resin bond at the cut face is already damaged by the cutter. The foil lifts, a trace neck cracks, or a plane corner delaminates a few tenths of a millimeter inward. None of that is visible until thermal cycling or vibration starts working the same spot.
Heavy copper (2 oz and above) makes this worse, not better. Thicker foil stores more residual stress and peels in a larger sheet when the edge bond fails.
Keep solid plane copper away from tab locations and V-score lines. If a plane must approach the edge, pull it back farther at the tab and restore the pour only where the outline is a continuous routed edge.
Design Clearances That Survive a Normal FR4 Process
Numbers that hold up on standard 1.6 mm FR4, CNC routed, no edge plating:
- Outer copper (traces and pads) to finished outline: 0.40–0.50 mm preferred. 0.30 mm is the practical floor for a capable shop and a simple outline.
- Outer plane pour to outline: 0.50 mm minimum. Pull planes farther than traces.
- Inner copper to outline: 0.40 mm preferred. 0.25–0.30 mm only when the fabricator confirms inner-layer pullback and registration capability.
- Copper to V-score centerline: treat as a worse outline. Add another 0.15–0.20 mm beyond the routed-edge rule.
- Copper to breakaway tab: 0.50 mm or more, and do not run planes through the tab neck.
Tight outlines, castellated holes, and edge connectors are separate rules. They need a process note, not a copied clearance from a standard digital board.
If board area is so tight that 0.5 mm cannot be spared, the correct conversation is with the fabricator about routing method, panelization, and whether the edge will be plated or coated—not a silent reduction of copper-to-edge to 0.15 mm in the CAD rules.
FR4 PCB edge clearance is a process stack-up problem dressed up as a drawing dimension. Set the copper-to-board-edge rule to survive routing tolerance, depanel stress, and isolation—not to match the smallest number on a capability table. The boards that pass incoming inspection are the ones where the plane stopped short of the cutter.
