Thermal vias are the only practical way most FR4 boards move heat out of a power package. Without them the copper pour under a QFN or DPAK is just a local heat island. Junction temperature rises, derating starts early, and long-term reliability drops. The question is never "do I need thermal vias?" It is how many, where, and how they are actually fabricated.
Most layout problems with FR4 PCB thermal vias come from treating them like ordinary signal vias. That is the first mistake.
Why Thermal Vias Exist on FR4 and What They Actually Do
FR4 itself is a poor thermal conductor—roughly 0.3 W/m·K through the thickness. Copper is three orders of magnitude better. The only low-resistance path from a hot pad to a large copper plane or the opposite side of the board is a plated through-hole. That is the entire function of a thermal via.
A single 0.3 mm finished via with 25 µm average copper plating carries a thermal resistance on the order of 50–80 °C/W depending on board thickness. Ten of them in parallel drop that number into the single digits. That is why arrays matter more than individual via size.
Engineers sometimes skip the array because the component footprint looks clean without holes. The result is a pad that runs 20–40 °C hotter than the data sheet thermal model assumes. The model almost always assumes a populated via array connected to a solid plane.
Via Count and Pitch That Actually Move Heat
Count is not linear. The first four or five vias under a 5 × 5 mm pad do most of the work. Adding more continues to help, but the incremental gain falls off once the vias start competing for the same copper volume in the plane.
Practical density for most power packages: 0.8–1.0 mm center-to-center. Closer than about 0.65 mm and the drill process starts to risk breakout into adjacent copper or annular ring thinning. Wider than 1.2 mm and you leave large areas of the pad thermally isolated.
A 4 × 4 array (16 vias) on a 6 × 6 mm pad is common and works well. A 3 × 3 is the minimum most of us accept for anything dissipating more than 1–1.5 W. Below that the thermal resistance climbs fast.
Drill size itself is secondary. 0.25–0.35 mm finished hole is the usual range. Smaller holes plate less reliably on thick boards; larger holes steal too much copper from the pad and can cause solder voiding.
Thermal Via Placement Directly Under the Pad
Putting vias in the thermal pad is the right location. Putting open vias there is often the wrong process choice.
During reflow, molten solder is pulled down the barrel by capillary action. That solder is no longer available to form the joint. On fine-pitch QFNs the result is incomplete wetting or large voids under the pad. Both raise thermal resistance and create mechanical weak points.
Two common solutions exist. The first is to tent the vias with solder mask on the component side and leave the opposite side open or plugged. The second is to fill the vias with non-conductive or conductive epoxy and plate over them (via-in-pad). Via-in-pad is cleaner electrically and thermally, but it adds cost and requires the fabricator to control fill voiding.
If the design stays with open vias, keep the via diameter small (≤0.3 mm finished) and the pitch not tighter than 0.9 mm. That combination reduces the volume of solder that can be lost while still providing a usable thermal path.
Copper Area and Continuous Thermal Paths
Vias alone do nothing if they terminate in a small copper island. The heat has to spread. A solid plane on the layer the vias connect to is the minimum. Better is a plane that continues under the entire component and out to a larger copper region or to the board edge where convection or a heat sink can remove the energy.
Many layouts place a local pour under the pad, connect the thermal vias into it, and then break the pour with a narrow neck to the main ground plane. That neck becomes the thermal bottleneck. Keep the connection as wide as the pad itself whenever possible. If a neck is unavoidable, make it at least 3–4 times the board thickness in width.
On multilayer boards the internal planes do most of the spreading. Outer-layer copper helps mainly when the board is thin or when the opposite side is used as a heat-sink mounting surface. In that case the thermal vias must reach the outer layer and the outer copper must remain continuous under the mounting area.
Copper weight matters more than people expect. 1 oz copper is adequate for most signal boards; 2 oz on the thermal planes drops spreading resistance noticeably. Going beyond 2 oz helps less than simply adding more vias or improving the plane continuity.
Fabrication Limits That Change Thermal Via Performance
Aspect ratio is the first manufacturing constraint. On a 1.6 mm board a 0.25 mm drill already sits at 6.4:1. Many shops can plate that reliably; some cannot. When the board thickens to 2.0 mm or more, move to 0.3 mm minimum finished hole or accept reduced plating thickness in the barrel.
Plating thickness variation is real. Specifying "25 µm minimum average" still allows local thin spots. Those thin spots raise thermal resistance and become the first locations to crack under thermal cycling. For high-reliability work, request a cross-section coupon with measured barrel copper.
Via fill quality is another variable. Non-conductive fill that leaves a void under the pad creates a thermal void and a mechanical stress riser. Conductive fill improves thermal performance but must be compatible with the subsequent plating chemistry. Not every fabricator offers both options with consistent results.
Solder mask tenting over thermal vias is never perfect. Small openings still appear. If the design relies on tenting to prevent solder wicking, inspect the first article under magnification. Incomplete tents are a common DFM finding.
Practical Layout Rules That Survive Production
Start with the component thermal model. Most data sheets give θJA or ψJT assuming a specific via pattern. Match that pattern first, then improve it if board real estate allows.
Keep the thermal vias inside the pad outline by at least 0.15 mm from the pad edge. This preserves annular ring and reduces the chance of drill breakout into the solder mask dam.
Connect every thermal via to a continuous copper plane. Do not leave floating vias or vias that only touch a small local pour.
If the opposite side of the board is used for heat sinking, bring the vias all the way through and keep the outer copper solid under the contact area. Adding a thin thermal interface material later will not compensate for a broken copper path.
For designs that must stay with open vias, limit the via diameter and increase the number rather than using a few large holes. Solder loss scales with via volume; thermal conductance scales with the square of the plated diameter and the number of vias.
Finally, treat thermal via design as part of the stack-up discussion, not an afterthought during layout. Once the board thickness and copper weights are fixed, the maximum useful via density is already constrained. Changing it later usually means a respin.
Good FR4 PCB thermal via design is mostly about continuity and process compatibility. Get those two right and the temperature rise stays predictable. Ignore either and the part runs hotter than the simulation ever showed.
