Most via failures on FR4 boards start with a simple decision: the designer picks a finished hole size and then draws a pad that looks "big enough." That pad is rarely big enough once drill wander, plating thickness, and etch undercut are stacked on top of each other. The result is annular-ring breakout, thin plating at the knee, or vias that crack after a few thermal cycles.
FR4 PCB via size and FR4 PCB via pad size are not independent numbers. They form a tolerance stack that the fabricator has to live with every day. Get the relationship wrong and the board either fails DFM or fails in the field.
How Via Structure Actually Behaves on FR4
A via is three things at once: a drilled hole, a plated barrel, and a copper land on each layer. The finished hole diameter is the drill size minus twice the copper plating thickness. Typical electrolytic copper is 20–25 µm per side after process variation. So a 0.30 mm drill usually finishes around 0.25–0.26 mm.
The pad diameter must leave enough copper outside that finished hole after registration error. That leftover copper is the annular ring. On outer layers the minimum acceptable ring for IPC-6012 Class 2 is 50 µm; Class 3 wants 75 µm. Most shops prefer 100 µm or more because the real process capability is tighter than the standard allows.
Inner-layer pads are more critical. The drill hits the inner copper after the stack is already pressed, so any mis-registration eats the ring from both sides. Thin rings on inner layers are the classic source of open vias that only appear after thermal stress.
Why the Pad Must Be Larger Than the Drill by a Fixed Margin
The relationship is mechanical, not aesthetic. Drill position tolerance on a typical FR4 panel is ±50 to ±75 µm. Hole-size tolerance is another ±25 µm. Etch factor on the outer copper removes another 10–20 µm from the pad edge. Add those three numbers and a "minimum" 50 µm ring disappears.
A practical rule that survives most fabs: finished hole + 0.25 mm for the pad diameter on outer layers when the board is ≤1.6 mm thick. For 2.0 mm and thicker boards the same pad often needs +0.30 mm because aspect-ratio plating is less uniform and drill wander increases.
If the design is dense and you are forced to smaller pads, the only safe path is to tighten the fabrication call-out: specify Class 3 annular ring, require X-ray drill registration, and accept the cost adder. Otherwise the fabricator will simply reject the panel or plate it and hope.
Manufacturing Limits That Force Larger Vias Than the Schematic Suggests
Aspect ratio is the first hard stop. Standard FR4 drills and plating baths are comfortable up to 8:1 or 10:1 (board thickness divided by drill diameter). A 1.6 mm board with a 0.20 mm drill is already 8:1. Many shops will accept it, but plating thickness at the center of the barrel drops and voids become likely. Push past 12:1 and you are into sequential-lamination or laser-via territory, which changes the whole cost structure.
Minimum drill size is the second stop. Most FR4 production lines still quote 0.20 mm finished as the reliable floor for through-holes. 0.15 mm is possible but requires specialized drill bits, higher spindle speeds, and more frequent bit changes. Yield drops and the price rises. Below that you are looking at microvias.
Plating uniformity also degrades with small holes. The copper at the knee of the via is thinner; thermal cycling then concentrates stress exactly where the copper is weakest. That is why vias with undersized pads or high aspect ratios show intermittent opens after a few hundred cycles even though the initial continuity test passed.
Choosing FR4 PCB Via Size by Function
Signal vias can stay small. For ordinary digital or low-speed analog, a 0.25–0.30 mm finished hole with a 0.50–0.55 mm pad is adequate on 1.6 mm FR4. The current is low, so plating thickness is not critical and density is usually the driver.
Power vias are different. Current capacity is limited by the cross-section of the plated barrel. A 0.30 mm finished hole with 25 µm copper carries roughly 1 A continuously with modest temperature rise. Parallel vias or a larger diameter (0.40–0.50 mm) are needed once the current climbs. The pad must grow with the hole or the annular ring collapses.
Thermal vias under a QFN or power package are usually 0.30 mm finished on a 0.55–0.60 mm pad, arrayed on a 1.0–1.2 mm grid. Smaller holes fill better with solder or epoxy, but the thermal resistance rises. Larger holes conduct heat better but risk solder voids if the via is not tented or filled.
High-voltage designs add another constraint. Creepage and clearance rules may force the pad-to-pad spacing to increase, which indirectly limits how small the via can be if the board real estate is fixed.
Practical Pad and Hole Combinations That Survive Production
For standard 1.6 mm FR4, four combinations cover most work:
- 0.20 mm finished / 0.45 mm pad – density-critical signal only, Class 3 required
- 0.25 mm finished / 0.50 mm pad – general digital and low-power
- 0.30 mm finished / 0.55–0.60 mm pad – mixed signal and moderate power
- 0.40–0.50 mm finished / 0.70–0.80 mm pad – power and thermal
Always check the fabricator's published capability chart before locking the numbers. A shop that drills 0.15 mm every day will accept tighter rings than one that runs mainly 0.30 mm and larger. The same design that passes at one house will be flagged at another.
When the stack-up is thicker than 2.0 mm, increase every pad by at least 50 µm and re-evaluate aspect ratio. Plating throw into deep holes is never as good as the data sheet suggests.
What Breaks When the Dimensions Are Wrong
Annular-ring breakout is the most common DFM rejection. The drill exits the pad edge; the plating either opens or becomes a thin whisker that fails under thermal expansion. FR4 expands more in the Z-axis than copper; the mismatch repeatedly stresses the thin copper at the breakout point until it cracks.
Even when the ring looks intact, high-aspect-ratio vias with undersized pads show higher resistance after reflow or after temperature cycling. The plating is thinner at the center of the barrel and the knee is already stressed by the pad edge being too close.
Solder wicking into an untented via during assembly can also starve a nearby SMT joint if the pad is large and the hole is open. That is a secondary effect, but it appears often enough that tenting or plugging should be specified when the via sits under a BGA or fine-pitch component.
Design Rules That Keep FR4 Vias Reliable
Start every layout with the fabricator's minimum annular-ring and aspect-ratio numbers, not with the IPC minimums. Add 25–50 µm of extra ring for process variation. Keep finished hole size ≥0.25 mm unless density absolutely forces smaller. Match pad diameter to hole diameter so the ring never falls below 100 µm on outer layers and 75 µm on inner layers for Class 2 work.
For power and thermal vias, calculate current or heat first, then choose the hole, then grow the pad. Never shrink the pad to "save space" after the hole is already fixed.
Document the finished hole size, not the drill size, on the fabrication drawing. Fabricators plate to the finished size; calling out the drill creates an unnecessary ambiguity that shows up as yield loss later.
The right FR4 PCB via size and FR4 PCB via pad size are the ones that survive the tolerance stack, the plating process, and the thermal cycles the product will actually see. Everything else is just geometry that looks good on the screen.
