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How Are FPC Boards Tested Before Shipment? Electrical, AOI and Reliability Checks Explained

Author : Alex Chen | PCB Design & High-Speed Engineering Specialist

August 05, 2026


In production we never ship an FPC lot without 100% electrical testing for opens and shorts, followed by AOI on the copper pattern and coverlay, then final visual inspection under magnification. Reliability checks—dynamic bend, thermal shock, and coverlay adhesion—are run on a sampling basis according to the application class. These FPC testing methods form the last gate before packaging; CAM and QA treat them as non-negotiable for any flexible PCB inspection sequence.

 Side-by-side process flow showing a panel of FPCs moving from flying-probe or fixture electrical test station into AOI camera

Why flex construction forces these extra gates before the boards leave the line

Polyimide and adhesive systems move more than FR-4 during lamination, etching and coverlay press. Copper traces that look continuous on the artwork can develop micro-cracks after the material relaxes, and coverlay openings shift relative to pads because of differential expansion. Flying-probe or bed-of-nails fixtures therefore have to accommodate that dimensional change; a rigid-board test program simply will not seat properly. AOI lighting also has to be adjusted—flex surfaces reflect differently and coverlay bubbles or wrinkles create false positives that rigid-board algorithms miss. These material behaviors are why the same electrical and visual criteria that work on rigid boards are insufficient for flexible PCB inspection.

Panelization constraints add another layer. FPCs are often nested tightly on a panel with break-away tabs or laser-routed outlines. Any residual stress left after routing can open a near-open that only appears after the board is flexed in the customer's assembly. That is why we run electrical test after final outline and after any stiffener attachment rather than earlier in the process.

What actually shows up downstream when any of these checks are skipped or under-sampled

Missed opens or high-resistance nets surface as intermittent failures on the customer's functional tester, usually after the board has already been assembled. Coverlay voids or mis-registration that AOI should have caught allow solder wicking or flux entrapment; those defects only become visible after reflow or after the first few flex cycles in the field. Edge delamination or copper burrs that escape visual inspection create shorts once the board is folded into the final product housing. In high-volume runs we have seen entire lots returned because a single untreated coverlay adhesion issue propagated through the reel. Scrap cost is secondary; the real hit is the schedule delay while the customer waits for a replacement lot that has to be re-processed from copper-clad laminate.

Close-up photographs of three typical escape defects

How the factory sequences electrical, AOI and reliability work in real production

Electrical test comes first. For volumes under a few hundred pieces we use flying-probe systems programmed with the netlist extracted from the Gerber or ODB++ data. Probe force is limited so the soft polyimide is not permanently indented. Above a few thousand pieces we build a dedicated fixture; the fixture design includes vacuum hold-down and floating probes that compensate for the ±0.1 mm typical dimensional variation of an FPC panel. Continuity threshold is normally set at 20–50 Ω depending on trace length and copper weight; isolation is checked at 10–50 MΩ. Any board that fails is marked and pulled for microscopic verification before it can re-enter the lot.

AOI follows immediately after electrical test. Cameras are set for both bright-field and dark-field illumination so that coverlay wrinkles, adhesive squeeze-out and copper undercut are all visible. The system compares against the same CAM data used for etching; we intentionally tighten the tolerance on pad-to-coverlay clearance by 25–50 µm relative to the customer's drawing because the material will continue to move slightly after the board is cut from the panel. Defects that AOI flags are reviewed by an operator under a stereo microscope; true defects are either repaired (if the design allows) or scrapped.

Final visual inspection is still 100 %. Operators check outline quality, stiffener alignment, surface cleanliness and any residual adhesive at the edges. Magnification is typically 10× for general surfaces and 20–40× for fine-pitch areas or gold fingers. This step also catches any handling damage introduced after AOI.

Reliability sampling is layered on top. For consumer-grade FPCs we pull 3–5 pieces per lot for a 180° bend test (usually 10–20 cycles) and a basic thermal-shock sequence (–40 °C to +85 °C, 5–10 cycles). Automotive or medical grades raise the sample size and the cycle count; dynamic bend to 10 000–20 000 cycles and thermal shock to 100–500 cycles become typical. Coverlay peel strength is measured on coupons taken from the same panel. These results are logged against the lot traveler so that any process drift is visible before the next run starts.

Where the factory can relax the full sequence without creating unacceptable risk

Prototype or engineering-sample lots under 50 pieces often skip dedicated fixture electrical test and run only flying-probe plus reduced AOI sampling; the customer accepts the residual risk in exchange for faster turnaround. Low-cost consumer applications that will never see repeated flexing can drop dynamic bend testing and keep only a single thermal-shock cycle. When the board carries no high-current nets and the copper is 1 oz or heavier, isolation resistance limits can be loosened. In every case the decision is documented on the traveler and the customer is informed before the lot ships. Medical, automotive or any board that will be dynamically flexed in the final product stays on the full inspection path—no exceptions.

The combination of 100 % electrical test, AOI tuned for flex materials, visual edge inspection and application-specific reliability sampling is how we keep field returns low while still moving production volume. Designers who understand these FPC testing methods and the limits of flexible PCB inspection can set realistic acceptance criteria and avoid last-minute surprises at the factory gate.

Alex Chen | PCB Design & High-Speed Engineering Specialist Alex Chen | PCB Design & High-Speed Engineering Specialist

Alex Chen is a senior PCB design engineer with extensive experience in high-speed and high-density circuit design. He specializes in signal integrity, impedance control, and multilayer PCB layout optimization. At AIVON, he reviews and refines content related to PCB design principles, EDA tools, and advanced layout techniques. His expertise helps engineers avoid common design pitfalls and improve performance, reliability, and manufacturability in complex PCB projects.

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