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HDI Via Stub Problems: When Do They Actually Affect Signal Performance?

Author : Alex Chen | PCB Design & High-Speed Engineering Specialist

August 18, 2026


 

A via stub is simply the unused portion of a plated hole that extends past the layer where the signal transitions. In many HDI designs the stub is short enough that it never becomes an electrical problem. In others it is long enough to create a clear impedance discontinuity and a resonant notch that sits inside the signal bandwidth. The difference is not theoretical. It is a function of stub length relative to the rise time and the frequency content of the signal.

Most layout discussions treat every via stub as a problem that must be eliminated. That approach wastes routing resources and fabrication cost on signals that do not care. The practical question is simpler: when does the residual HDI via stub actually move the eye or degrade the insertion loss enough to matter?

 

How Via Stubs Form in Typical HDI Constructions

In a pure microvia HDI stack the transition is usually from the surface to layer 2 or from layer 2 to layer 3. The via ends at the capture pad. There is no unused length below the signal layer, so the stub is essentially zero. That is one of the main electrical advantages of sequential build-up.

Stubs appear when the design mixes microvias with through vias or buried vias that span more layers than the signal needs. A signal that enters on layer 1, drops to layer 6 through a through via, and then continues on layer 6 leaves the remaining plated length from layer 6 to the bottom of the board as a stub. The longer the unused portion, the larger the discontinuity.

Back-drilling can remove most of that unused copper, but residual stub length still remains. Typical residual after controlled-depth drilling is 0.15–0.25 mm. In thick boards that residual can still be electrically significant at higher data rates.

HDI Via Stub

 

Stub Length Relative to Signal Rise Time and Frequency

The electrical length of the stub is what matters, not the physical millimeter count by itself. A useful first-order check is to compare the round-trip delay of the stub to the signal rise time. When the stub delay approaches or exceeds roughly one-third of the rise time, reflections begin to distort the edge and close the eye.

At higher frequencies the stub behaves as an open-ended transmission line resonator. The first resonance typically appears near the quarter-wave frequency of the stub length. For a 1.5 mm residual stub in FR-4 the quarter-wave notch sits around 25–30 GHz, well above most current digital rates. Shorten the rise time or lengthen the stub and that notch moves downward into the signal spectrum.

In practice, stubs shorter than 0.5 mm rarely affect signals below 8–10 Gbps on common dielectrics. Stubs longer than 1.5–2 mm begin to show measurable impact on 10 Gbps and above, especially when the via is already a significant impedance discontinuity.

 

Impedance Discontinuity and the Visible Signal Effects

Even a short stub adds a capacitive load at the via transition. The plated barrel and the stub together lower the local impedance. On a 50 Ω differential pair the dip can be several ohms. The reflection coefficient is small at low frequency but grows as the edge rate increases.

When the stub is long enough to resonate inside the bandwidth, a notch appears in the insertion-loss curve. That notch reduces the available amplitude at the receiver and can create deterministic jitter. The effect is more pronounced on longer channels where the signal has already lost margin to dielectric and conductor loss.

In HDI the via itself is often smaller and the pad stack tighter than in conventional boards. That reduces the baseline discontinuity, so a residual stub of the same physical length produces a smaller absolute impedance excursion than the same stub on a large through via. The relative impact is still governed by length versus rise time.

HDI Via Stub Analysis

 

When Stub Control Becomes Necessary

For the majority of digital signals running below 5 Gbps, residual stubs of 1 mm or less are electrically invisible. Power nets, low-speed control lines, and most memory interfaces outside the highest-speed data groups do not require stub management.

Control becomes relevant once the data rate or the edge rate pushes the spectral content toward the stub resonance or makes the capacitive discontinuity large relative to the rise time. Typical thresholds seen in practice:

PCIe Gen3 and similar 8 Gbps interfaces: stubs longer than ~1 mm begin to consume margin on longer channels.

10–16 Gbps SERDES: residual stubs should be held under 0.5–0.7 mm or removed.

25 Gbps and above: near-zero stub transitions (microvia or carefully back-drilled) are usually required.

The decision is also channel-dependent. A short, well-terminated link tolerates more stub than a long backplane-style channel that already operates near the loss budget.

 

Practical Methods to Keep Stubs Under Control in HDI

The cleanest solution is architectural: route high-speed signals using only microvia transitions that terminate at the signal layer. Sequential build-up HDI makes this straightforward for the outer layers. For signals that must reach deeper layers, buried vias or staggered microvia stacks can still keep the unused length short.

When through vias are unavoidable, controlled-depth back-drilling remains the standard method. Specify the maximum residual stub length the signal can tolerate and verify the fab's process capability. Typical production residuals of 0.15–0.25 mm are acceptable for many 10–16 Gbps applications; tighter control is needed at higher rates.

Via-in-pad with filled microvias eliminates both the stub and the breakout trace, removing two discontinuities at once. This approach is common on high-density HDI packages and is electrically preferred when the fabrication process supports it.

a high-speed signal routed with pure microvia transitions

 

Design Judgment Rather Than Blanket Rules

Not every HDI via stub needs to be driven to zero. The electrical impact scales with length and with the frequency content of the signal. Applying the most aggressive stub-removal techniques to every net increases cost and complexity without improving performance on the majority of the board.

The practical approach is to classify nets by edge rate and channel length, then apply stub control only where the residual length would interact with the signal. For the rest of the design, normal HDI via practices are sufficient. That distinction keeps the layout efficient and the fabrication process within normal capability while still protecting the signals that actually care about the HDI via stub.

Alex Chen | PCB Design & High-Speed Engineering Specialist Alex Chen | PCB Design & High-Speed Engineering Specialist

Alex Chen is a senior PCB design engineer with extensive experience in high-speed and high-density circuit design. He specializes in signal integrity, impedance control, and multilayer PCB layout optimization. At AIVON, he reviews and refines content related to PCB design principles, EDA tools, and advanced layout techniques. His expertise helps engineers avoid common design pitfalls and improve performance, reliability, and manufacturability in complex PCB projects.

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