This 118 × 138 mm single-layer copper base board with 380W thermal conductivity and direct heatsink pads required detailed capability assessment on two critical manufacturing constraints. The thermoelectric separation structure necessitated use of our conventional stackup rather than the customer-provided documentation, and limited achievable ENIG gold thickness to 0.05µm due to direct electrical connection between edge pads and base copper.
Thermoelectric Separation Structure and Stackup Selection
Thermoelectric separation designs feature a direct thermal and electrical interface between the copper circuit layer and the aluminum base through a controlled dielectric. In this configuration, the edge pads connect electrically to the base copper, creating a large thermal mass that fundamentally changes how surface finish and lamination processes behave. The customer documentation included a specific stackup that did not align with the physical requirements of this architecture.
During this single-layer copper base board ( #CU-20260120-022 ) engineering review, we evaluated the provided stackup against our standard stackup for thermoelectric separation boards. The conventional stackup uses optimized dielectric thickness and bonding parameters proven to deliver consistent thermal conductivity above 380W while maintaining AC2500V insulation performance. Deviating from this proven configuration would introduce unacceptable risk to both thermal transfer efficiency and high-voltage reliability. After confirming dielectric spacing, copper distribution, and aluminum base interface integrity, we recommended proceeding with the conventional stackup.
Figure 1: the stackup shown in the document
Figure 2: our standard stackup for thermoelectric separation boards
| Stackup Element | Customer Documentation | Conventional Stackup | Capability Assessment |
|---|---|---|---|
| Dielectric Thickness | Variable per drawing | Optimized for thermal path | Selected for 380W conductivity |
| Copper to Aluminum Interface | Not fully defined | Controlled bonding | Ensures AC2500V insulation |
| Thermal Conductivity Target | 380W | Proven achievable | Maintained with conventional parameters |
The decision to use the conventional stackup was driven by process repeatability data. In previous thermoelectric separation builds, this configuration consistently delivered uniform dielectric thickness and void-free interfaces. Any deviation increases the probability of localized thermal resistance or insulation breakdown under high-voltage stress. First-article cross-sections were planned to verify interface quality before volume production.
ENIG Gold Thickness Limitation Due to Base Copper Connection
A critical constraint identified during engineering review was the customer requirement for 0.5mm gold thickness in the ENIG finish. In standard ENIG processing, gold is deposited in the range of 0.05–0.5µm. A specification of 0.5mm represents an extremely thick layer that far exceeds normal plating capability and is physically unrealistic for immersion gold processes.
The thermoelectric separation structure exacerbates this issue significantly. Because the edge pads are electrically and thermally connected to the large base copper layer, the copper mass functions as a substantial heat sink during the immersion plating process. This rapidly draws heat away from the pad surfaces, slowing the gold reduction reaction and severely limiting the achievable deposition thickness.
Process capability evaluation confirmed that under these conditions, the maximum reliable and uniform gold thickness achievable is 0.05mm. Attempting to reach even a fraction of the requested 0.5mm would require excessively long immersion times, leading to risks such as inconsistent coverage, nickel layer degradation, and potential damage to fine features. The 0.05mm gold thickness remains functionally adequate for oxidation protection and solderability in high-power thermal applications when paired with a properly controlled nickel underlayer.
ENIG Gold Thickness Limitation Due to Base Copper Connection
A critical constraint identified during engineering review was the customer requirement for 0.5mm gold thickness in the ENIG finish. In standard ENIG processing, gold is deposited in the range of 0.05–0.5µm. A specification of 0.5mm represents an extremely thick layer that far exceeds normal plating capability and is physically unrealistic for immersion gold processes.
Figure 3: the gold thickness cannot reach 0.5 mm
The thermoelectric separation structure exacerbates this issue significantly. Because the edge pads are electrically and thermally connected to the large base copper layer, the copper mass functions as a substantial heat sink during the immersion plating process. This rapidly draws heat away from the pad surfaces, slowing the gold reduction reaction and severely limiting the achievable deposition thickness.
Process capability evaluation confirmed that under these conditions, the maximum reliable and uniform gold thickness achievable is 0.05mm. Attempting to reach even a fraction of the requested 0.5mm would require excessively long immersion times, leading to risks such as inconsistent coverage, nickel layer degradation, and potential damage to fine features. The 0.05mm gold thickness remains functionally adequate for oxidation protection and solderability in high-power thermal applications when paired with a properly controlled nickel underlayer.
| ENIG Gold Thickness | Customer Requirement | Process Capability | Engineering Assessment |
|---|---|---|---|
| Requested Thickness | 0.5mm | Not achievable | Far exceeds standard ENIG limits |
| Achievable Thickness | — | Maximum 0.05mm | Limited by heat sink effect of base copper |
| Risk at Higher Thickness | High | Inconsistent coverage, nickel damage | Not recommended |
In this case, the combination of an unusually thick customer specification and the inherent thermal mass of the thermoelectric separation structure created a clear process capability boundary. Proceeding with 0.05mm gold thickness represents the realistic and controllable manufacturing window while still meeting functional requirements for the application.
In this case, the combination of an unusually thick customer specification and the inherent thermal mass of the thermoelectric separation structure created a clear process capability boundary. Proceeding with 0.05mm gold thickness represents the realistic and controllable manufacturing window while still meeting functional requirements for the application.
Interaction Between Stackup and Surface Finish Processes
The choice of conventional stackup directly influences surface finish outcomes. A dielectric layer optimized for thermal conductivity also affects heat dissipation during plating. Our conventional stackup parameters were reviewed to ensure they would not exacerbate the heat sink effect during ENIG processing. Minor adjustments to pre-plating cleaning and activation steps were implemented to improve gold deposition consistency on the connected copper regions.
According to IPC-6012 guidelines for metal core boards, surface finish thickness on large copper masses must be evaluated for functional performance rather than nominal specifications. The 0.05µm gold layer, combined with a properly controlled nickel underlayer, meets solderability and environmental protection requirements for this application class.
Validation of Stackup and Gold Thickness Decisions
First-article production included comprehensive verification of both critical parameters. Cross-sectional analysis confirmed dielectric thickness and interface quality consistent with the conventional stackup. XRF measurements verified gold thickness at 0.05µm across multiple locations, including edge pads directly connected to base copper. Electrical testing confirmed AC2500V insulation performance, and thermal path evaluation supported the 380W conductivity target.
All EQ communications regarding stackup selection and gold thickness limitation were resolved through documented engineering justification and customer confirmation prior to volume release. The 17-day delivery schedule accommodated the additional verification steps required for these special-process features.
| Validation Item | Method | Target | Result |
|---|---|---|---|
| Stackup Dielectric | Cross-section | Conventional parameters | Compliant |
| Gold Thickness | XRF | 0.05µm | Achieved uniformly |
| Insulation Performance | High-voltage test | AC2500V | Passed |
Conclusion
The thermoelectric separation copper base board was approved for production after rigorous evaluation of the two primary constraints: adoption of the conventional stackup for reliable thermal and insulation performance, and acceptance of 0.05µm gold thickness as the practical limit imposed by base copper connection. Both decisions were grounded in process capability data and validated through first-article testing. This case illustrates how material architecture directly dictates achievable process windows in specialized PCB manufacturing.
FAQs
Q1: Why must the conventional stackup be used instead of customer-provided documentation for thermoelectric separation boards?
A1: The conventional stackup has been validated through multiple production builds to deliver consistent dielectric thickness, void-free interfaces, and reliable thermal conductivity above 380W while maintaining high-voltage insulation. Deviations increase risk of thermal resistance or electrical breakdown.
Q2: Why is gold thickness limited to 0.05µm in ENIG on thermoelectric separation structures?
A2: Edge pads connected directly to the large base copper act as a heat sink during immersion plating. This slows gold deposition and makes higher thicknesses difficult to achieve uniformly without introducing other defects.
Q3: Does 0.05µm gold thickness still provide adequate solderability and protection?
A3: Yes, when combined with a properly controlled nickel underlayer. For power and thermal management applications, 0.05µm gold meets functional requirements for oxidation protection and solder joint formation.
Q4: How does stackup choice affect surface finish processing?
A4: Dielectric thickness and bonding parameters influence heat dissipation during plating. The conventional stackup was reviewed to ensure it would not further limit gold deposition uniformity on connected copper areas.
Q5: What verification is performed when changing to a conventional stackup?
A5: Cross-sectional analysis confirms dielectric thickness and interface quality. High-voltage testing and thermal path evaluation are also performed to ensure the board meets both insulation and conductivity specifications.
