Can a Via Be Placed in a Pad? A Detail PCB Designers Cannot Skip

Via-in-Pad in PCB Design: Electrical Benefit Versus Soldering Risk

Via-in-pad comes up often among both new and experienced PCB designers. The usual question is whether a via can sit directly in a surface-mount pad, and what happens if it does. The electrical argument is straightforward: placing the via in the pad shortens the connection and reduces lead inductance. The manufacturing argument is equally direct: the same structure can steal solder from the joint and create defects that only appear after reflow.

The practical answer is that via-in-pad is possible in theory and often undesirable in practice unless the via is fully plugged and plated as part of a controlled process. For most layouts, pulling the via just off the pad and connecting it with a short trace is the more reliable choice.

Possible in Theory, Not Preferred in Practice

Two points define the trade-off.

First, from an electrical standpoint, a via in the pad gives the shortest lead and the lowest lead inductance, so the connection is allowed. In high-speed or high-frequency layouts, that shortest path can look attractive. Any extra length between a pad and its via adds a small series inductance. At sufficiently high edge rates or frequencies, that inductance can affect signal quality or the local impedance of a power connection. Putting the via in the pad removes that extra segment.

Figure 1 | Structure of a via placed in a pad

Second, from the soldering process, the same structure can cause serious defects. If the via is not fully plugged, solder paste can run into the hole during reflow. The pad is then left with too little solder, the joint can go cold, or the component can lift. The electrical ideal and the process reality therefore point in opposite directions unless the fabrication process is specifically prepared for via-in-pad.

The distinction matters. A via that is drilled, plated, and left open is a capillary path for molten solder. A via that is plugged, planarized, and capped can occupy a pad with far less risk. When the board house has not been asked to plug and plate the via, treating an open via-in-pad as electrically convenient is a manufacturing gamble.

Common Defects: Solder Wicking and Tombstoning

Solder wicking

Solder wicking is the most common process failure associated with an unplugged via in a pad. During reflow, the paste becomes liquid. Surface tension and capillary action pull that liquid into the barrel of the via. Paste that was intended to form a fillet on the component termination instead disappears into the hole.

After cooling, the pad is short of solder. The joint may look incomplete, the mechanical strength may be too low, or the electrical connection may be intermittent. In severe cases the component termination is left sitting on a starved pad with little or no fillet. Because the defect is created by the open via itself, inspection after assembly often finds the problem only after the board has already gone through reflow.

The risk increases when the via is large relative to the pad, when the paste volume is modest, or when the via opens to the opposite side of the board and provides an easy escape path for molten solder. Fully plugging the via closes that path. Leaving it open invites wicking.

Tombstoning

Tombstoning is a related SMT defect. When the two ends of a chip component heat unevenly, paste on one side can melt and wet first. Unbalanced surface tension then stands the part up on one termination.

Figure 2 | Tombstoning, with one end of the part lifted

A via in one pad of a two-terminal chip part is a typical trigger. If that via wicks solder, that end of the part loses paste volume and may wet later or more weakly than the opposite end. The stronger fillet pulls the body upright. The result is a component standing on one end, often called the Manhattan effect.

This failure is especially common on chip resistors and capacitors. Those parts are light, their terminations are small, and a modest imbalance in solder volume or wetting time is enough to lift one end. Once the part has tombstoned, the open end is an electrical open and the assembly must be reworked.

Uneven heating can contribute even without a via, but an unplugged via-in-pad makes the imbalance more likely because it systematically removes solder from one pad. That is why via location on small chip components is treated as a process issue, not only a routing convenience.

Lead Inductance and Tombstoning

Two terms sit at the center of the decision.

Lead inductance describes the inductive reactance of the conductor between a component pad and the rest of the net. In a high-frequency or high-speed circuit, that short lead is a common source of parasitic inductance. It can degrade high-speed signaling or local power integrity by adding impedance that was not present in the schematic. In theory, the lead should be as short as possible, which is the electrical argument for via-in-pad.

Tombstoning, or the Manhattan effect, describes the soldering failure in which unequal force at the two ends of a chip part lifts one end and the joint fails. It is a process argument against leaving an open via in the pad of that part.

These two concerns are not contradictions so much as constraints that must be satisfied together. The layout can keep inductance low without placing an open hole in the solderable area. The usual method is a very short trace from the pad to a nearby via.

Preferred Practice: Pull the Via Off the Pad

Balancing theory and process, the preferred layout is to pull the via out of the pad and connect it with a short trace. The extra length is small. The reduction in process risk is large.

The benefits are direct:

• Lead inductance stays small because the connecting trace is short.
• Process defects from solder wicking into an open via are avoided.
• Solder volume on the pad remains available for the joint, so yield rises.

The short trace should be treated as part of the pad-to-via transition, not as an arbitrary dog-bone drawn at any length. Keeping that segment brief preserves most of the electrical advantage of via-in-pad while leaving a solid, closed copper pad for the solder paste. The via can then be tented or left open on the opposite side without draining the joint.

When a design truly requires via-in-pad, for example under a fine-pitch BGA where escape routing leaves no room for a dog-bone, the fabrication note should call for plugged and plated vias so the pad surface remains planar and closed. That is a process commitment, not a silent assumption. Without that commitment, an open via in a pad remains a soldering risk.

Layout is not only drawing a net. It has to carry signal, electrical, and manufacturing constraints together. Via location looks like a small choice. It still decides whether the joint has enough solder, whether a chip component stays flat, and whether the board solders and ships cleanly.