8-layer PCB high-speed routing becomes practical once the design carries DDR, PCIe, and USB at the same time. The extra planes give every critical net a continuous ground reference without forcing the high-speed pairs onto layers that also carry components or power splits. A workable arrangement is Signal / Ground / Signal / Ground / Power / Signal / Ground / Signal. Outer layers stay microstrip; inner signal layers can run as stripline between grounds. That combination keeps return current local and impedance more stable than a 6-layer board can manage when pin density and edge rates both rise.
The stackup only helps if the routing rules treat the reference plane and the via as part of the net, not as afterthoughts.
Stackup Choices That Support Multiple High-Speed Interfaces
Put the fastest differential pairs on layers that reference solid ground on at least one side, preferably both. Outer microstrip works for short runs to connectors. Inner stripline between two grounds contains the field better and reduces crosstalk, but it adds dielectric loss and makes probing harder. Keep the dielectric height to the nearest ground in the 3–6 mil range for most 85–100 Ω targets. Thicker cores force wider traces that eat channels; thinner prepreg raises cost and tightens the impedance window the fabricator can hold.
Power planes can sit next to ground for interplane capacitance, but do not use a split power plane as the primary reference for multi-gigabit edges. The return still has to reach ground.
DDR Routing: Length Matching and Topology
DDR data, strobe, and address/command lines need tight length matching within the byte lane and across the fly-by chain. On FR-4 the delay is roughly 150–170 ps per inch on microstrip; inner layers are slightly slower. A 10–20 ps budget therefore allows only a few mils of mismatch before serpentine is required. Keep the serpentine at least 3× trace width from the pair so it does not create extra coupling. Address and command usually run fly-by with short stubs to each device; long stubs ring.
Route the entire byte lane on the same layer when possible. Layer changes introduce via delay that is hard to match exactly. Continuous ground under the entire run is non-negotiable. A split under the address bus converts differential energy into common mode and collapses the timing margin at the corner.
PCIe Differential Pairs, Impedance, and Insertion Loss
PCIe Gen3/4 targets 85 Ω differential with tight skew, typically a few mils. Calculate width and gap for the actual dielectric height and copper thickness; do not copy geometries from a different stackup. Keep the pair together on the same layer with identical via structures. Inter-pair spacing of 5× or more reduces lane-to-lane crosstalk. Insertion loss grows with length and with dielectric loss; on standard FR-4 the practical length for Gen4 is limited. Low-loss materials help, but the via transitions and connectors usually dominate the budget before the dielectric does.
Every layer change needs a nearby ground stitch via so the return follows the signal. Without it the return spreads and the differential-to-common conversion increases.
USB High-Speed and SuperSpeed Routing
USB 2.0 is relatively forgiving at 90 Ω differential. USB 3.x SuperSpeed pairs tighten the skew budget to a few mils and the impedance window to ±10%. Route the SSTX and SSRX pairs with consistent gap, same layer, and minimal vias. Length should stay as short as the connector and controller placement allow. Continuous ground reference is required for the entire length; a plane split under the pair creates both reflection and radiation that the cable then radiates further.
Keep the pairs away from clocks and switching regulators. Orthogonal routing on adjacent layers reduces broadside coupling when the pairs must run near other high-speed nets.
Differential Pair Geometry and Length Matching
Width, gap, and height to the reference plane set differential impedance. On a typical 8-layer stack with 4–5 mil dielectric to ground, 100 Ω pairs often land around 4–5 mil width and 5–8 mil gap; 85 Ω pairs are slightly wider or closer. Match length within the pair to the interface skew limit. Match groups of pairs to the timing budget of the link. Serpentine for matching should stay clear of the pair and of other pairs. Any asymmetry in via count or pad size between the two members of a pair converts differential energy into common mode.
Layer Transitions, Via Stubs, and Reference Changes
Every via adds a discontinuity. On an 8-layer board a through-via from an outer layer to an inner layer leaves a stub that can resonate in the multi-gigabit range. Keep stubs as short as possible. Back-drilling removes the unused portion when the data rate is high enough that the stub length approaches a significant fraction of the wavelength. Blind vias eliminate the stub but raise cost and require process capability the fabricator must confirm.
When the signal changes layers the reference usually changes too. Place a ground stitch via within a few millimeters of the signal via so the return current can jump planes without spreading. For differential pairs, place the stitch vias symmetrically. Missing the stitch via is one of the most common causes of intermittent eye closure on 8-layer PCB high-speed routing.
Crosstalk and Return Path Control Between Interfaces
DDR, PCIe, and USB pairs need spacing that grows with edge rate and parallel length. On outer microstrip, 5× trace width is a common minimum between pairs; inner stripline can run closer because the planes contain the field. Avoid long parallel runs between different interfaces. Orthogonal routing on adjacent signal layers cuts broadside coupling. Continuous ground under every pair keeps the return local so the pairs do not share a long common path that converts noise into common mode.
Verification Before and After Fabrication
Calculate impedance for the production stackup and confirm with the fabricator's coupon. Run SI simulation on the critical nets—length matching, via discontinuities, and crosstalk—before layout freeze. Post-layout DRC should catch plane splits under high-speed nets and missing stitch vias. On the prototype, measure eye diagrams at the corners and check radiated emissions. Most failures that appear only on the built board trace back to a return path that looked continuous in the CAD view but was interrupted by a via antipad cluster or an unstitched layer change. On 8-layer PCB high-speed routing the stackup gives the margin; the routing either preserves it or spends it on vias and plane discontinuities.
