Multilayer PCB impedance control starts with the dielectric height to the nearest reference plane, not with the trace width you draw in the CAD tool. Width, copper thickness, and Dk all matter, but a 10% change in dielectric thickness moves impedance more than most etch variation. On a 4-layer board the outer layers are microstrip over the nearest plane. On 6- and 8-layer boards you also have stripline options between planes. The calculation only holds if the reference stays continuous under the net and the finished geometry matches what the fabricator actually builds.
Most impedance problems show up as reflections that close the eye or as TDR coupons that sit outside the ±10% window after etch and lamination.
What Actually Sets Characteristic Impedance
Single-ended impedance is the ratio of voltage to current for a forward-traveling wave on one trace over a reference plane. Differential impedance is the same idea between two traces. Both drop when the trace gets wider, the copper gets thicker, the dielectric gets thinner, or the Dk rises. On FR-4 with Dk around 4.2–4.5, a 50 Ω microstrip over a 4–5 mil dielectric often lands in the 6–10 mil width range for 1 oz copper. Thicken the dielectric to 8 mil and the same width jumps toward 60 Ω or higher. You compensate by widening the trace or accepting a different target.
Soldermask on outer layers lowers effective Dk slightly and shifts impedance a few ohms. Inner layers do not see that shift. Calculate for the finished stackup, not the nominal core thickness.
Stackup and Reference Plane Distance
The dielectric thickness between the signal layer and its nearest continuous reference plane is the dominant term. On a standard 4-layer stack the outer signals sit over a thin prepreg to the ground or power plane. That gives relatively wide traces for 50 Ω. On 6- and 8-layer boards you can choose thinner prepreg under outer layers for tighter impedance control or thicker cores for mechanical strength. Inner signal layers between two planes become stripline; the total dielectric height between the planes sets the impedance, and the field is fully contained.
Any split or void under the trace forces the return current to detour. The local impedance rises and a reflection appears. Keep the reference continuous under every controlled-impedance net for its entire length.
Microstrip Versus Stripline on Multilayer Boards
Outer-layer microstrip is easy to probe and connects directly to components, but part of the field is in air so the effective Dk is lower and the trace is wider for a given impedance. Stripline between two planes has a higher effective Dk, so the trace is narrower for the same impedance, and the field is shielded. Crosstalk is lower and radiation is reduced, but dielectric loss is higher and you cannot probe the trace without a via. On 4-layer boards almost all controlled nets stay microstrip. On 6- and 8-layer boards you can put the most sensitive pairs on inner stripline layers if the stackup provides continuous ground on both sides.
Impedance Control by Layer Count
Four-layer boards typically control impedance only on the outer layers. Bottom-layer nets reference the power plane, so any power split under those nets creates an impedance discontinuity. Six-layer boards add at least one inner signal layer that can reference solid ground on one or both sides. Eight-layer boards give multiple stripline options and tighter dielectric control on more layers, which helps when several multi-gigabit interfaces share the board. In every case the fabricator needs the target impedance, the layer, and the differential gap if applicable. Specifying only a width without the stackup leaves the result to process variation.
Single-Ended and Differential Targets
Single-ended targets are usually 50 Ω for most digital interfaces. Differential targets vary: 100 Ω for many Ethernet and HDMI pairs, 90 Ω for USB, 85 Ω for PCIe. The differential impedance depends on both the individual trace geometry and the gap between the two traces. Closer spacing lowers differential impedance and increases coupling. Calculate both single-ended and differential for the same stackup; the fabricator will adjust width and gap together. Keep the pair on the same layer with identical via structures. Any asymmetry converts differential energy into common mode.
How Geometry and Material Tolerances Move the Result
Etch undercut narrows the finished trace. On 1 oz copper the undercut is typically 0.5–1 mil per side, so a 6 mil artwork line may finish near 4–5 mil. That raises impedance. Fabricators compensate by widening the artwork; the coupon verifies the compensation. Dielectric thickness varies with resin flow and lamination pressure. A 10% thickness change can move impedance several ohms. Dk also varies lot to lot on standard FR-4. Low-loss materials hold Dk more tightly but cost more. Copper plating adds thickness on outer layers and lowers impedance slightly for a given width. All of these effects stack. Specifying ±10% is common and achievable; ±7% or tighter raises cost and requires process feedback the fabricator must confirm.
Vias, Stubs, and Reference Changes
A via is a short transmission-line discontinuity. The pad capacitance and the stub inductance both create reflections. On multilayer boards a through-via from an outer layer to an inner layer leaves a stub that can resonate at multi-gigabit rates. Back-drilling removes the unused stub when the data rate makes the length significant. Blind vias eliminate the stub but add cost. When the signal changes layers the reference plane usually changes too. Place a ground stitch via next to the signal via so the return can follow without a long detour. Missing that stitch via creates both an impedance bump and a radiation source.
Coupons, TDR, and What the Measurement Actually Proves
The fabricator builds impedance coupons on the same panel using the same stackup, copper weight, and etch process. TDR measures the finished impedance of those coupons. A passing coupon within ±10% confirms that the process hit the target for that geometry. It does not prove that every net on the board has continuous reference or that every via transition is clean. The coupon is a straight trace over solid copper. Real nets have pads, vias, and occasional plane openings. Review the coupon report against the stackup notes, then still check plane continuity and stitch vias on the critical nets.
Common Causes of Impedance Failures
The usual findings are a reference plane split under a controlled net, etch compensation that was not applied or was applied incorrectly, dielectric thickness that drifted outside the assumed range, and via stubs or missing stitch vias that the coupon never saw. Width variation from panel edge to center also appears on large boards. On multilayer PCB impedance control the stackup and the continuous reference set the baseline. Process variation and layout discontinuities either stay inside the tolerance or push the result outside it. Specify the targets clearly, confirm the stackup with the fabricator, and verify both the coupon and the actual return path under the fastest nets.
