PMU PCB Design in Practice: Multi-Rail Power Splitting and Plane Integrity

These problems appear often in PMU circuits:

• A schematic that looks correct still shows unexplained voltage ripple after power-up
• Power parameters that were calculated carefully still miss the design target in measurement
• The system restarts under specific operating conditions, with no clear fault location

In high-speed PCB design, the power management unit (PMU) often determines system stability. The most demanding part of that work is splitting multiple power rails while keeping power-plane integrity. This article uses hardware project experience to cover the core points of PMU layout and a practical method for power-plane splitting.

1. Core Challenges in PMU Power Management

1.1 Power Complexity in Modern Systems

As SoC integration increases, power requirements become more complex:

• Multiple voltage domains coexist: CPU core voltage, I/O voltage, analog voltage, memory voltage, and others
• Dynamic voltage scaling adjusts voltage and frequency with load
• Large transient current demand: inrush during processor start-up or a sudden load step can reach tens of amperes

1.2 Why Power Integrity Matters

Power integrity (PI) is the ability of the power delivery network to supply stable, clean power to the ICs. A poor power design can cause:

• Excessive voltage ripple, which disturbs IC operation and can collapse the system
• Electromagnetic interference (EMI), with the power plane acting as a radiation source and affecting other circuits
• Signal integrity problems, when power noise couples into signal nets

2. Practical Strategies for Multi-Rail Power Splitting

2.1 Basic Rules for Power Splitting

The purpose of power splitting is to isolate different voltage domains while keeping the power path low-impedance.

1. Split by voltage level
   • Isolate high-voltage domains from low-voltage domains completely
   • Place an isolation gap between analog power and digital power
2. Split by current magnitude
   • Give high-current power planes a wider path
   • Account for via current capacity to avoid overheating from overcurrent
3. Split by noise sensitivity
   • Give sensitive analog circuits a separately split power plane
   • Isolate high-speed digital circuits from low-frequency circuits

2.2 Three Common Power-Splitting Methods

Method 1: Physical Separation

Applicable when different voltage domains or noise-sensitive circuits must be fully isolated.

• Implementation: use a split line in the PCB tool to separate the power planes completely
• Advantage: isolation is strong and power-noise coupling is reduced effectively
• Notes
  • The split line must be continuous, with no gaps
  • Signals that cross the split region need special treatment
  • Do not place sensitive components next to the split line

Method 2: Groove Separation

Applicable when some isolation is needed but routing flexibility must be kept.

• Implementation: cut an isolation groove in the power plane instead of splitting it completely
• Advantage: provides a useful amount of isolation while keeping routing more convenient
• Notes
  • Groove width should be at least 20 mil and adjusted for board thickness and signal frequency
  • Do not place vias or components in the groove
  • Avoid routing critical signals across the groove

Method 3: Capacitive Coupling Separation

Applicable when two power domains need AC coupling and DC isolation.

• Implementation: place high-frequency coupling capacitors between the two power planes
• Advantage: AC energy can pass while DC voltages stay isolated
• Notes
  • Select the capacitor value from the signal frequency
  • Place the capacitors close to the nets that need coupling
  • Account for capacitor parasitics and their effect on the signal

2.3 Practical Splitting Techniques

1. Plan the power planes before signal routing
   • Decide the split scheme early in the design
   • Place components according to the power-plane layout
2. Use plane connections instead of traces
   • A power plane has much lower impedance than a trace
   • High-current paths must use plane connections
3. Place power layers and ground layers correctly
   • Keep a power layer tightly adjacent to a ground layer to form a low-impedance power loop
   • Place critical power planes next to their corresponding ground layers

3. Key Elements of Power-Plane Integrity

3.1 Power-Plane Impedance Control

Target impedance is a core parameter of the power design:

Z_target = V_ripple / I_transient

• V_ripple: maximum allowed voltage ripple
• I_transient: maximum transient current

Example calculation: if the CPU core voltage is 1.0 V, allowed ripple is 50 mV, and maximum transient current is 10 A, then:

Z_target = 0.05 V / 10 A = 5 mΩ

3.2 Decoupling Capacitor Selection and Placement

Decoupling capacitors are required to keep the power impedance low.

1. Capacitor type
   • Ceramic capacitors: high-frequency decoupling (above 100 MHz)
   • Electrolytic capacitors: low-frequency decoupling (below 1 MHz)
   • Tantalum capacitors: mid-frequency decoupling
2. Capacitance combination
   • Place several values in parallel to cover a wide frequency range
   • A typical set: 10 μF + 1 μF + 0.1 μF + 0.01 μF
3. Placement rules
   • Place decoupling capacitors next to the IC power pins
   • Keep the vias from the capacitor to the power plane and ground plane as short as possible
   • Do not put vias or other components between the capacitor and the IC

3.3 Power-Plane Integrity Checklist

Key checks for power-plane integrity:

• Does the power plane have unnecessary splits or openings?
• Are high-current paths wide enough?
• Is decoupling-capacitor placement reasonable?
• Does the spacing between the power plane and the ground plane meet the impedance requirement?
• Are signals that cross a split region handled correctly?

4. Common Mistakes

4.1 Mistake 1: Finer Splits Are Always Better

Excessive splitting breaks plane continuity and raises impedance.

• Problem: too many splits destroy plane integrity and increase the impedance of the power path
• Correction
  • Judge the real isolation need between domains and avoid unnecessary splits
  • Domains with similar noise levels can share a plane
  • Use ferrite beads or 0 Ω resistors to connect regions that need digital-ground isolation

4.2 Mistake 2: More Decoupling Capacitors Are Always Better

Too many decoupling capacitors can create resonance problems.

• Problem: when a capacitor self-resonant frequency lines up with a PDN resonance, impedance can rise sharply
• Correction
  • Calculate capacitor self-resonant frequencies and avoid stacking resonances
  • Combine different values and packages
  • Use simulation to optimize the capacitor set

4.3 Mistake 3: Ignoring Current Distribution on the Power Plane

The high-current path directly affects power efficiency and reliability.

• Problem: current on a power plane is not uniform; it concentrates on the shortest path
• Correction
  • Size plane width from current density
  • Avoid via arrays on high-current paths; use a continuous solid plane where possible
  • Include temperature when judging plane current-carrying capacity

5. Case Study: PMU Design for a High-Performance Processor

5.1 Project Background

A PMU design for a high-performance AI processor included:

• Six voltage domains (0.8 V–3.3 V)
• Maximum total current above 50 A
• Strict EMI and ripple limits

5.2 Design Challenges

1. Isolation between multiple power rails
2. Low-impedance design of high-current paths
3. Compliance with a strict radiated EMI limit

5.3 Solution

1. Power-splitting strategy
   • The core voltage domain (0.8 V) was fully isolated from the other domains
   • Analog power used an independently split plane
   • I/O voltage domains shared a plane, with ferrite beads isolating different regions
2. Plane-integrity design
   • An 8-layer stackup was used, with four layers assigned to power and ground
   • The spacing between the core power plane and its ground plane was kept within 4 mil
   • High-current paths used additional copper thickening
3. Decoupling optimization
   • Each processor power pin had three decoupling capacitors of different values
   • Board-level decoupling used a mixed-value set covering 10 kHz–1 GHz
   • A power-integrity simulation tool was used to optimize capacitor placement

5.4 Test Results

• Voltage ripple stayed within 2% (well below the 5% industry figure cited for this case)
• Radiated EMI passed Class B
• The system passed a 72-hour continuous-run stability test

6. Summary

1. Power-splitting strategy: choose the split method from voltage level, current magnitude, and noise sensitivity
2. Plane integrity: keep the power plane continuous and control the impedance of the power path
3. Decoupling design: select and place capacitors so they cover a wide frequency range
4. Verification: confirm the result with simulation and measurement

Three steps for improving a PMU layout:

1. Review the current design
   • Check the power plane for unnecessary splits
   • Measure power ripple and noise
   • Review decoupling-capacitor placement
2. Revise the design
   • Adjust the split scheme using the methods above
   • Optimize the capacitor combination and placement
   • Verify the changes with simulation
3. Measure and iterate
   • Build a test board and measure it
   • Compare data before and after the change
   • Continue until the design requirements are met

PMU layout is a core hardware skill. Multi-rail splitting and plane integrity are the difficult parts of that work. Understanding power-integrity principles, applying a practical split method, and checking the result in measurement are what produce a stable, efficient power system. Because hardware designs differ, the same method still needs adjustment and verification on the actual product.