A clean simulation report can still fail on the bench. Respins, delay, and a failed bring-up often follow. Most of that gap comes from how the simulation was run. These are the mistakes that show up most often in signal-integrity work.
Mistake 1: Treating Time-Domain and Frequency-Domain Simulation as Interchangeable
Some engineers run only the time domain or only the frequency domain and treat one plot as enough. That is a gap.
Time-domain simulation shows what the waveform looks like, how open the eye is, and whether overshoot or undershoot is present. It is a snapshot of the result.
Frequency-domain simulation shows behavior versus frequency, S-parameter curves, and impedance matching. It is closer to a diagnostic report of the underlying structure.
The two views complement each other. The time domain shows the result. The frequency domain shows the cause. A closed eye without frequency-domain analysis leaves no locator. An S-parameter sweep can point to the frequency where the channel fails.
Run both, and set the sweep from the signal rate. For DDR4 at 3200 Mbps, the simulation frequency needs to go above 5 GHz before the result is useful. On current AI-server 112G SerDes links, a sweep above 40 GHz is the safer range.
Figure 1 | Time-domain versus frequency-domain simulation
Mistake 2: Judging an Eye Only by How Open It Looks
The first look at a simulated eye is often only whether the opening is large. A large opening is treated as pass. A small opening is treated as fail. That is only the first reading.
Besides eye height and eye width, these parameters matter as well:
- Jitter: excessive jitter makes the receiver sample the wrong data. Separate RJ and DJ. Many faults sit in DJ.
- Rise time / fall time: an edge that is too slow distorts a high-speed signal. The 10%-90% rising edge should not exceed 20% of a UI.
- Eye crossing percentage: a large shift away from 50% is duty-cycle distortion and can break receiver clock recovery.
- Eye mask: any mask hit is a hard fail, no matter how open the eye looks.
Mistake 3: Judging PDN Design by Capacitor Count Instead of Impedance
Power integrity is a PDN (power delivery network) impedance problem. Adding more decoupling capacitors is often treated as enough. The impedance curve then shows peaks across the band.
Typical causes include the wrong capacitor self-resonance, anti-resonance from paralleled values, and layout inductance that is too high. Any one of them can drive impedance out of the target.
AI devices and advanced packages make PDN work harder. HBM currents of tens of amperes mean a small supply disturbance can take the die out of a valid operating region. Last year an AI training card from a major vendor went through a batch rework after the PDN design was insufficient.
More capacitors are not automatically better. Calculate the target impedance first, choose values whose resonances sit in the right places, and only then optimize placement.
Figure 2 | PDN impedance analysis and resonance identification
Mistake 4: Treating Right-Angle Corners as Harmless
On a low-speed net a right-angle corner may not matter. At high speed, millimeter-wave frequencies, or multi-Gbps rates, that corner is a problem.
A right-angle corner adds parasitic capacitance of about 3-5 fF. The number looks small. At high frequency it still steps the impedance and reflects the edge. Enough reflection closes the eye.
The fault can look mild in time-domain simulation if the model is not accurate enough. The built board then shows it. That is a common simulation-to-lab gap.
Use a 45-degree miter or an arc. Keep the corner length at least twice the trace width. On a differential pair, turn both traces together or skew appears.
Mistake 5: Ignoring the Via Stub
Multilayer boards need vias. Stub length is often ignored on the assumption that a buried unused length does not matter.
A stub behaves like an antenna. Part of the signal energy reflects from it and shows up on the eye as a ghost image that compresses the opening.
Above 16 Gbps the stub can no longer be ignored. In 112G PAM4 simulation, a via stub longer than 8 mil already makes the channel eye difficult to accept.
Keep high-speed stubs inside 10 mil. Above that length, back-drill. On a 112 Gbps PAM4 high-speed backplane the stub effect is larger still. The extra process cost is lower than a respin.
Figure 3 | Incorrect design versus correct design
A Sounder Simulation Sequence
- Set the signal rate and the simulation band before the run. Do not shrink the sweep to save time.
- Use time-domain and frequency-domain results together and cross-check them.
- Read the full eye: not only height and width.
- On PDN simulation, watch the impedance curve and stay off resonance peaks.
- Optimize the high-speed path end to end, including corners and vias.
- Use vendor models. Do not leave default models in place on a critical net.
Simulation is not finished when the tool draws a plot. The result has to be read: what the curves mean, which way they trend, and where the channel actually fails.
