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Stack-up Principles for Multilayer PCB Design

Author : Alex Chen | PCB Design & High-Speed Engineering Specialist

September 11, 2026


In a multilayer PCB, the stack-up is one of the controlling decisions. A poor stack-up shows up directly in product performance: crosstalk between layers, radiated emission, warped boards, and a power distribution network whose impedance is higher than the design assumed. The rules below are the ones used when the layer order is set.

 

Keep Each Signal Layer Next to a Ground Plane

Keep each signal layer next to a ground plane. An adjacent ground plane reduces crosstalk and radiated emission between signals. The plane supplies the return path and shields radiation from the signal layer. On high-frequency and high-speed boards, an adjacent ground plane also avoids split-plane crossings. Important signals should therefore be routed on a signal layer that sits next to ground.

Signal layer placed next to a ground plane in a multilayer stack-up

A high-speed edge does not return through a distant ground pin. It returns on the nearest reference plane, immediately under the trace. If that plane is continuous ground, the loop area stays small, coupling to neighboring nets falls, and less energy is available to radiate. If the adjacent layer is another signal layer, or a power plane that is split into islands, the return has to detour. That detour is crosstalk and emission.

Split-plane crossings are the practical failure of this rule. When a trace runs from over one plane region onto another, the adjacent reference changes. The return current cannot follow the trace across the gap. It finds a longer path, often through a decoupling capacitor or a distant via, and the trace sees an impedance break. Routing important signals on a layer that already sits next to solid ground removes that crossing from the layer assignment instead of trying to route around it later.

Keep the Stack-Up Symmetric

Keep the PCB stack-up symmetric. Symmetry affects how much the finished board bows. An asymmetric stack-up warps after fabrication, which then hurts SMT yield and can produce weak or cold solder joints.

Copper and dielectric do not shrink the same way through lamination and cool-down. If thick copper or a dense plane sits on one side of the centerline and a thin signal layer sits on the other, the board bows or twists as it leaves the press. A warped board does not sit flat on the solder pallet. Paste thickness varies, component leads do not meet the pads evenly, and joints can be weak or cold even when the footprint is correct.

Symmetry here means a balanced construction about the center of the stack: similar copper weights, similar dielectric thicknesses, and plane layers mirrored rather than piled on one half of the board. Electrical layer order still has to satisfy the return-path rules. The mechanical constraint is that those electrical choices should not leave one side of the board much heavier than the other.

 Symmetric versus asymmetric multilayer PCB stack-up

Set the Layer Next to the Components as a Ground Plane

Set the layer next to the components as a ground plane. That plane shields the parts and keeps outer-layer signals from crossing a split. Crossing a split means a signal's adjacent reference changes across more than one plane region.

Outer layers carry components, short escape traces, and sometimes high-speed routes that could not be buried. The plane immediately under those layers is the reference those routes and those component pads actually see. Making that plane ground gives the parts a continuous shield and gives outer-layer signals one reference instead of a patchwork of power islands.

A power shape used as the first inner layer forces every outer trace to change reference wherever the shape ends. That is the split crossing: the adjacent reference is no longer one plane. Ground as the layer next to the components avoids that change for the nets that are hardest to bury.

 

Place a Power Plane Next to a Ground Plane

Place a power plane next to a ground plane whenever possible. The two planes form a planar capacitor and lower the impedance of the power plane.

A power-ground pair separated by a thin dielectric is a distributed capacitor spread across the board. High-frequency current that would otherwise travel to a distant decoupling capacitor can return through that pair. The result is a lower impedance on the power plane at the frequencies where discrete capacitors have already gone inductive.

Separating power and ground by several signal layers removes that capacitance. The planes still connect at decoupling parts, but the path between them is longer and the plane impedance is higher. Putting the pair together does not replace local decoupling at IC pins. It gives the plane itself a return that discrete parts cannot provide across the whole board.

Power plane adjacent to ground forming planar capacitance

 

Avoid Adjacent Routing Layers in Parallel

Avoid two adjacent layers that route in parallel. Crosstalk between parallel routing layers is high and degrades signal quality and board performance. Broadside coupling between two traces stacked on neighboring layers is stronger than edge coupling between traces on the same layer, because the facing area is the full trace width and the dielectric between them is often thin.

If two routing layers must sit next to each other, run one layer horizontal and the other vertical, or increase the dielectric between them to open the spacing. Orthogonal directions keep long parallel runs from forming, so the coupled length stays short even where traces cross. A thicker dielectric between the two signal layers reduces the capacitance that couples them. Both fixes are concessions. The preferred stack still puts ground between signal layers so the coupling path is a plane, not another trace.

That is the idea behind the so-called dummy eight-layer stack-up. Extra layers are added so that signal layers can each sit against ground, power can sit against ground, and two routing layers are not left face to face with only a thin dielectric between them. The added layers are not there to fill a routing quota. They are there so the five rules above can be true at the same time: signal against ground, a symmetric build, ground next to the components, power against ground, and no long parallel broadside pair.

Layer order is fixed before routing starts. A stack that violates these rules cannot be repaired by a cleaner trace. Crosstalk, emission, warp, and power-plane impedance are already built into the press.

Alex Chen | PCB Design & High-Speed Engineering Specialist Alex Chen | PCB Design & High-Speed Engineering Specialist

Alex Chen is a senior PCB design engineer with extensive experience in high-speed and high-density circuit design. He specializes in signal integrity, impedance control, and multilayer PCB layout optimization. At AIVON, he reviews and refines content related to PCB design principles, EDA tools, and advanced layout techniques. His expertise helps engineers avoid common design pitfalls and improve performance, reliability, and manufacturability in complex PCB projects.

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