EMC Design Starts with Early Planning
Many engineers who design DC-DC power supplies have experienced the same problem: the prototype performs normally, meets its efficiency and performance targets, and then fails EMC testing repeatedly. The subsequent redesigns, PCB revisions, and debugging cycles can consume substantial time and engineering resources.
The most effective EMC solution is rarely a late-stage corrective measure. It begins with system architecture and PCB layout planning from the start of the design.
Every EMC problem can be traced to three fundamental elements: the noise source, the coupling path, and the susceptible device. The corresponding solutions are to suppress the noise source, interrupt the coupling path, and protect the sensitive device.
In a DC-DC system, the power converter itself is often the most significant electromagnetic noise source. Therefore, the most direct way to address EMC problems is to suppress the noise generated by the DC-DC converter at its origin.
Using the widely adopted buck converter as an example, this article examines two primary noise sources: the high-frequency current loop, which produces magnetic-field interference, and the high-frequency switching node, or SW node, which produces electric-field interference. The discussion also covers practical PCB layout, component-selection, and shielding techniques for reducing conducted and radiated emissions.
Two Major Noise Sources in a Buck Converter
Most EMI noise in a switching power supply originates from the rapid changes associated with switching transients, particularly high di/dt current transitions and high dv/dt voltage transitions.
A buck converter contains two major high-frequency noise sources. They correspond primarily to magnetic-field and electric-field radiation and are common causes of excessive emissions in CISPR 25 automotive power testing and conventional industrial-control power-supply radiated-emissions testing.
1. The High-Frequency Current Loop: A Magnetic-Field Noise Source
The input-side switching loop carries a trapezoidal current waveform. Its current slope changes rapidly, and its rich high-frequency harmonic content produces a strong time-varying magnetic field. This is a typical near-field magnetic interference source.
By comparison, the current through the inductor is generally triangular. Its di/dt changes more gradually, so it contains fewer high-frequency components. The trapezoidal current generated by MOSFET switching, however, undergoes much more abrupt transient changes.
Measurements made with a near-field magnetic probe show that the magnetic-field strength near the upper and lower MOSFETs is much greater than that around the inductor, particularly at higher frequencies.
This is why power-supply EMC optimization should focus primarily on the high-frequency current loop formed by the switching devices rather than on the inductor freewheeling loop.
2. The High-Frequency SW Node: An Electric-Field Noise Source
The SW node in a buck converter experiences a high-speed square-wave voltage transition with a large dv/dt. This produces a strong time-varying electric field that can radiate into the surrounding space.
A critical detail is often overlooked: the inductor is not necessarily at a stable potential. It can also experience substantial voltage variation and therefore contribute to electric-field interference. In single-rod antenna radiated-emissions testing, the electric-field interference associated with the inductor can be particularly noticeable and may become an important cause of excessive high-frequency radiation.
Suppressing Noise from the High-Frequency Current Loop
The high-frequency current loop can be treated as a magnetic dipole. Its magnetic moment and magnetic-field strength increase with both current and loop area. In practical terms, magnetic interference can be reduced by lowering the high-frequency current or, more effectively in many layouts, by minimizing the loop area.
The current is normally determined by the required output power and cannot be reduced arbitrarily. As a result, PCB layout should concentrate on identifying and minimizing the loop in which the current changes most rapidly.
The high-frequency loop differs among converter topologies:
- In a buck converter, it is formed by the input capacitor and the two switching devices, or by one switching device and one diode.
- In a boost converter, which is the dual topology of a buck converter, the high-frequency loop is associated with the output capacitor and the two switching devices.
- In a SEPIC converter, the high-frequency loop is formed by the two switching devices and two capacitors.
Figure 1 | High-frequency current loops in several converter topologies
In general, the high-frequency loop consists of the switching devices and the capacitor connected to them. The current changes most abruptly as it commutates between the switching devices. Because inductor current cannot change instantaneously, the inductor naturally limits its own di/dt and is not usually the primary region of interest when analyzing the high-frequency switching loop.
After the high-frequency loop has been identified, the most effective way to reduce its near-field magnetic field is to minimize its physical area. The current must still meet the power-delivery requirements, so reducing the current is usually not a practical design variable.
Input-Capacitor Placement
The location of the input capacitor is especially important when reducing high-frequency loop area. Placing the capacitor on the back side of the IC, thereby reducing the distance between the capacitor and the switching devices, produces substantially lower measured noise than placing the capacitor beside the IC or connecting it through relatively long traces or leads.
Advances in packaging have also made it possible to integrate the input capacitor into the IC package. This can further reduce the high-frequency loop area and improve EMC performance.
When two devices, one with an integrated capacitor and one without, are tested using the same IC type and PCB layout, the device with the integrated capacitor exhibits lower high-frequency noise in the conducted portion of CISPR 25 testing. The smaller internal loop provides a significant advantage during conducted-emissions testing.
Using the PCB Reference Plane to Reduce Magnetic Coupling
PCB layout can also help suppress noise from the high-frequency current loop by using copper on the layer below the loop. According to Lenz's law, an induced current flows in a direction that opposes the change in magnetic flux that produces it.
If the high-frequency current loop is located on the top layer, it generates a magnetic field. A conductive copper region directly beneath it can develop an induced current and an opposing magnetic field, partially canceling the field generated by the current loop. The closer the continuous copper region is to the high-frequency loop, the stronger the potential reduction in magnetic coupling.
However, the lower copper region must be connected to ground through a sufficiently low-impedance path. If it is left electrically floating or connected poorly, it can become another coupling structure and may increase, rather than reduce, radiated emissions.
Suppressing Noise from the High-Frequency Switching Node
The buck converter also contains the high-frequency SW node discussed earlier. Its large dv/dt generates an electric field and can produce radiated emissions. It also drives common-mode current, which can be a significant component of conducted-emissions measurements, particularly during CISPR 25 testing.
The SW node is frequently associated with radiated emissions, especially in single-rod and biconical-antenna testing. During a single-rod antenna test, the near-field electric field generated by the high-frequency switching node can couple directly into the antenna.
One way to reduce this interference is to minimize the physical area of the SW copper region. Reducing the area exposed to the high dv/dt voltage reduces the electric-field strength. The same principle applies to the inductor: reducing its physical size can reduce the electric-field contribution observed during single-rod testing. The inductor should not automatically be treated as a quiet node because its potential can vary significantly at high frequency.
When power requirements prevent a substantial reduction in inductor size, a shielded inductor can be considered. In this context, a shielded inductor means an inductor with an external metal shielding layer that is connected to ground. It should not be confused with a molded magnetic-shielded inductor whose shielding effect comes primarily from its integrated magnetic material and construction.
An integrated electric-field-shielded inductor generally includes a metal housing. The housing must be grounded during use to provide a stable reference potential and create an effective electric-field shield.
In single-rod antenna testing from 150 kHz to 30 MHz, a shielded inductor produced nearly 20 dB of suppression in the measured result. A metal shield can also be used to enclose the SW node and the inductor, provided that the shield is properly connected to ground.
Figure 2 | EMI suppression achieved with a shielded inductor
Reducing Common-Mode Current
Common-mode current can appear in both conducted- and radiated-emissions testing. It is particularly important during radiated testing, where common-mode current on cables and other conductive structures can become an efficient radiation mechanism.
Its suppression can be approached in three ways:
- Reduce the area of the high-dv/dt switching region and reduce the inductor size where practical, thereby lowering the electric-field strength.
- Shield the SW node and the inductor to provide the high-dv/dt noise sources with a stable reference potential and reduce capacitive coupling.
- Add a common-mode choke at the input to increase the impedance of the common-mode current path.
Effective EMI control in a buck converter begins with identifying the physical structures that carry rapidly changing current or voltage. Minimizing the hot-loop area addresses magnetic-field interference, while reducing SW-node area, controlling inductor electric-field coupling, and applying appropriate shielding address electric-field interference and common-mode current. These measures are most effective when incorporated into the initial PCB architecture rather than added after EMC testing has already revealed a problem.
