In multilayer PCB design, a common question arises: why should the power plane be set back relative to the ground plane? At first glance this can look like wasted board area. In reality, the setback is a practical electromagnetic compatibility (EMC) measure that reduces edge radiation from plane pairs. This practice is often summarized by the so-called 20H rule.
The Electromagnetic Mechanism Behind Plane-Edge Radiation
When high-frequency currents flow in a PCB, they create time-varying electric and magnetic fields. Between a power plane and a ground plane, those fields are primarily confined to the dielectric region separating the planes, forming a distributed capacitance. However, at the plane edges, the "cavity" defined by the power (PWR) plane and ground (GND) plane opens to free space. If the two planes end at the same outline, the electric field lines at the edge can fringe outward and couple energy into the environment. The edge behaves like a slot radiator, making the plane pair a potential source of electromagnetic interference (EMI).
Figure 1 | Illustration of electromagnetic radiation when the power plane and ground plane end at the same board outline.
When the power and ground planes are coextensive, the fringe fields at their periphery readily couple to the outside. The larger and more abrupt the field discontinuity at the edge, the stronger the potential radiated emission. This is especially relevant when the plane pair supports high di/dt currents from switching loads, or when the planes form part of the return path for high-speed signals. The practical question is: how can the field be contained within the board stackup rather than allowed to leak out at the edges?
Is Setting Back the Power Plane Effective?
The answer is yes. Setting the power plane back from the ground plane edge helps confine the electric field within the board's internal ground "cavity," reducing edge fringing and radiated emissions. Conceptually, by pulling the power plane inward, you keep most field lines terminating within ground metal that extends beyond the power plane perimeter, rather than letting them open into free space at the board outline.
Figure 2 | Comparison of field distribution when the power plane is coextensive with ground versus when it is set back inside the ground perimeter.
As shown, a coextensive PWR/GND pair allows fields to spread outward, increasing EMI risk. When the power plane is set back, most field lines close within the ground region, and external leakage is reduced. The ground plane acts like a shield around the power plane's edge, reducing the slot antenna effect at the board boundary.
What Exactly Is the "20H" Distance?
The 20H rule defines an approximate setback distance, not a fixed absolute number. In this context:
- H is the dielectric thickness between the power plane and the adjacent ground plane.
- 20H is twenty times that dielectric thickness, used as a guideline for how far to pull the power plane perimeter inboard relative to the ground plane edge.
Figure 3 | With a 20H setback, most of the electric field is contained and "shielded" by the ground plane region around the power plane edge.
Studies have reported that:
- A setback of approximately 20H can suppress around 70% of the radiated field associated with plane-edge fringing.
- A setback of approximately 100H can suppress around 98% of the edge-related radiation.
In other words, greater setback yields lower EMI. However, expanding the setback also consumes board area that could otherwise be used for routing or via fields, so it must be balanced against layout density and manufacturability constraints. The 20H figure is typically a pragmatic compromise between EMC effectiveness and layout feasibility.
Why Not Always Use 100H?
While a 100H setback sounds attractive on paper, most designs cannot support such a large inboard distance for the power plane. Practical limitations include:
- Stackup and outline constraints that dictate usable copper area for power distribution and current density.
- Loss of routing channels or via keepouts near board edges, which can complicate fan-out and layer transitions, or reduce mechanical robustness.
- Reliability, manufacturability, and layer-utilization trade-offs that make extreme setbacks undesirable.
In practice, many engineering teams choose a moderate setback such as approximately 20H or a fixed dimension like around 1 mm, depending on the stackup, dielectric thickness, and board size. The goal is to achieve a meaningful reduction in edge fields without unduly compromising layout flexibility.
Figure 4 | A common practical implementation is an inboard power plane edge of approximately 1 mm relative to the ground plane edge.
When and Where the 20H Rule Applies
The 20H rule is not universally applicable to all multilayer boards. It relies on a specific stackup context to be effective:
- The power plane in question should be an internal layer, not an outer copper layer.
- The plane should be tightly coupled to ground, with the layers directly above and below being ground planes (0 V). This creates a well-defined cavity for the field.
- Both ground planes should extend beyond the power plane perimeter by the chosen setback distance (e.g., 20H), forming a continuous metallic boundary around the PWR edge.
- An eight-layer or higher stackup is often preferred because it more easily accommodates the required ground-power-ground arrangement while leaving sufficient routing layers.
These conditions ensure the setback actually contains the field. If the power plane is adjacent to only one ground plane or is near a split, void, or cutout, the field can still escape or couple unpredictably, reducing the benefit of the setback.
Design Considerations and Practical Guidance
Understanding H in Real Stackups
H is the dielectric thickness between the power plane and its adjacent ground plane. In many stackups, the separation between a PWR-GND pair is small to create high interplane capacitance and low loop inductance. The 20H setback scales with this thickness: thinner dielectrics require less physical setback for the same 20H criterion, while thicker dielectrics imply larger setbacks in absolute distance. When multiple dielectrics or prepregs separate the planes, use the effective thickness between the specific PWR and its nearest GND reference.
Field Containment and Return Currents
The PWR-GND pair behaves like a parallel-plate structure that stores energy in the dielectric. High-frequency return current between the power delivery network (PDN) and ground flows as displacement current through this dielectric. At the periphery of the planes, discontinuities allow that displacement current to "spread" into free space as radiation. By extending ground beyond the power plane and setting the power plane back, the structure presents a longer and more confining path for field lines to terminate within ground copper rather than radiate outward. This is why the setback reduces plane-edge emissions.
Trade-offs With Routing and PDN Performance
Setting back a power plane reduces copper area at the edges, potentially increasing current density and local IR drop if the PDN is already tight. It may also constrain placement of stitching vias, decoupling capacitors, or high-current vias near the board periphery. Balance the setback with PDN requirements: where edge current densities are high, consider local exceptions or reinforce the PDN with wider copper, multiple feeds, or additional stitching vias while maintaining a setback elsewhere.
Complementary EMC Practices
- Maintain continuous ground at the outer boundary. Avoid gaps, splits, or large voids in the ground planes near the edges that would defeat the shield-like effect.
- Use stitching vias along the ground edge where practical to improve vertical continuity between ground layers and further suppress slot modes at the board boundary.
- Keep high di/dt sources and fast edge-rate signals away from the board periphery. Plane setbacks reduce radiation but do not eliminate emissions from poorly controlled current loops or discontinuities.
- Combine the setback with robust decoupling: short, low-inductance connections between decoupling capacitors and their return to ground help minimize the energy that excites cavity modes within the PWR-GND pair.
Limitations and Exceptions
The 20H guideline is most effective when the power plane is sandwiched between solid, unbroken ground planes that extend farther than the power plane outline. In stackups that do not provide this arrangement—such as outer-layer power pours, or where PWR is adjacent to a signal layer without a nearby ground reference—the benefit is reduced. Similarly, if ground planes are segmented, contain sizable keepouts, or are perforated by dense via fields without adequate stitching, edge fields may still leak despite a setback. In these cases, prioritize continuous ground references and return paths before relying on a geometric setback alone.
Conclusion
Setting the power plane back from the ground plane edge is not about aesthetics or arbitrary rules; it is a practical EMC optimization that reduces plane-edge radiation in multilayer PCBs. The 20H rule provides a workable target for that setback: approximately 20 times the dielectric thickness between the power and ground planes. In many designs, a setback around 20H or on the order of 1 mm is a reasonable compromise between EMI reduction and routing efficiency. Larger setbacks such as 100H can further reduce radiation but are rarely practical due to layout and PDN constraints.
Plan the stackup early to place power planes internally and sandwich them between ground planes. Extend the ground beyond the power plane periphery by the chosen 20H setback, and maintain ground continuity at the edges. By containing fields within the board structure, you improve EMC performance and increase the likelihood of meeting compliance requirements without late-stage redesign.
The more the power plane is pulled back relative to ground, the smaller the plane-edge emissions—subject to stackup feasibility and PDN demands. Applied judiciously, the 20H principle is a practical tool in the high-speed PCB engineer's EMI mitigation toolkit.
