As server signaling rates have increased from 10 Gbps to 112 Gbps and even 224 Gbps, including applications such as AI servers and 1.6T optical modules, via stubs have become a critical constraint on signal integrity. Back drilling is the primary manufacturing process used to reduce stub effects, and its accuracy directly affects high-speed signal transmission quality. This article examines stub-length control and inspection methods from a PCB manufacturing perspective.
Sources and Risks of Via Stubs
What Is a Via Stub?
In multilayer server PCBs, which typically contain more than 12 layers and commonly use 16- to 24-layer stackups, a through-hole via may carry a signal from the top layer to an inner layer. For example, a signal may travel from L1 to L6. The portion of the plated hole that continues below L6 to the bottom of the board does not carry the intended signal. This unused section of plated barrel is called a via stub, and its length may reach several millimeters.
During PCB backdrilling, a larger-diameter drill enters from the opposite side of the PCB and removes the unused portion of the plated barrel. The objective is to eliminate as much of the stub as possible while preserving the required electrical connection between the signal layer and the remaining via structure.
Three Major Effects of Via Stubs on High-Speed Signals
Quarter-Wavelength Resonance
A via stub is essentially an open-ended transmission-line segment. When the signal frequency corresponds to a quarter wavelength equal to the stub length, the stub can produce a very low impedance point. It then absorbs and reflects energy from specific frequency components on the main transmission line, creating severe insertion loss and a resonance notch in the frequency domain.
For an FR-4 PCB with a dielectric constant of approximately 4.0 to 4.5, a 0.5 mm stub may produce resonance near 10 to 12 GHz. This frequency range can fall within the Nyquist band of many 25 Gbps channels, making even a relatively short residual stub electrically significant.
Impedance Discontinuity
A stub introduces parasitic capacitance and inductance. The stated approximate values are 0.5 to 1 pF of capacitance and 0.3 to 0.5 nH of inductance per millimeter. These parasitic elements cause the via impedance to deviate from the intended design value. For example, a 100 Ω differential channel may experience a local impedance reduction to approximately 70 to 80 Ω at the via structure.
This discontinuity generates signal reflections and can increase deterministic jitter. The resulting waveform distortion reduces the available sampling margin and may degrade the eye opening at the receiver.
Electromagnetic Radiation
An untreated stub can behave as an unintended antenna and radiate electromagnetic energy. Depending on the channel structure and operating frequency, this radiation may contribute to electromagnetic interference and may make it more difficult for the finished product to pass compliance testing.
Relationship Between Data Rate and Stub-Length Tolerance
As signaling rates increase, the allowable stub length becomes progressively shorter. The following values represent the typical limits listed for different data-rate ranges:
| Data Rate | Typical Stub-Length Limit | Application or Note |
|---|---|---|
| <1 Gbps | <1.5 mm ±15% | |
| 10 Gbps | <0.8 mm ±10% | |
| 25 Gbps | <0.5 mm ±7% | |
| 56 Gbps | <0.3 mm ±5% | 800G optical-module applications |
| 112 Gbps | <0.2 mm ±3% | AI servers and 1.6T optical-module applications |
| 224 Gbps | <0.1 mm ±2% | Next-generation communications equipment |
These limits should be treated as application-specific control targets rather than universal requirements for every PCB design. The acceptable stub length depends on the channel architecture, material system, rise time, signaling format, and system-level signal-integrity budget.
Methods for Precisely Controlling Back-Drilled Stub Length
Key Factors Affecting Stub-Control Accuracy
From a manufacturing standpoint, accurate stub control involves four main challenges.
- Board-thickness uniformity: Variations in the thickness of individual layers can make the Z-axis compensation inaccurate. The stated overall thickness tolerance may be approximately ±0.1 mm, while the core and prepreg thicknesses should be controlled within approximately ±0.05 mm where the design requires tighter depth control.
- Drilling accuracy: Drill wear affects both hole diameter and depth stability. Diamond-coated drills may be used for demanding applications, with the stated service life reaching at least 2,000 holes under the specified process conditions.
- Stackup matching: An asymmetric stackup can make it difficult to establish a reliable depth reference. A symmetric stackup design and an 8 to 10 mil safety allowance above the target layer are recommended in the described process.
- Depth control: Machine calibration and real-time board-thickness measurement are required to compensate for variation between individual panels or boards.
Critical Process Measures for Depth Control
Back-Drilling Depth Calculation
Back-drilling depth is the central parameter used to control the remaining stub. The calculation is expressed as:
Back-drilling depth = total board thickness ? distance from the target back-drill layer to the drill-entry surface + compensation value
The compensation value accounts for actual board thickness and process-related variation. Incorrect stackup data, inaccurate thickness measurement, or an unsuitable reference surface can result in either excessive residual copper or damage to the intended signal connection.
CCD Vision Positioning
High-precision back drilling generally requires a drilling machine equipped with a CCD vision-positioning system. The vision system identifies the actual PCB position and detects positional deviation in real time. The machine then applies dynamic mechanical compensation. Positioning accuracy can reach within ±5 μm under the stated conditions.
This approach helps address hole-offset problems caused by PCB deformation, loading errors, and registration variation. Accurate XY positioning is especially important when the back-drill diameter is only slightly larger than the original plated through-hole and when the remaining annular structure has limited tolerance.
Three-Level Depth-Calibration System
- Startup calibration: A test drill is performed on a board with a known standard thickness to calibrate the Z axis. The stated calibration target is ±0.02 mm.
- Per-board compensation: The thickness of each board is measured with a laser before processing. The drilling depth is then adjusted in real time to compensate for board-to-board thickness variation.
- In-process verification: After every 50 boards, two boards are randomly selected for depth inspection. If the deviation exceeds ±0.03 mm, the machine is stopped for investigation and adjustment.
Electrical Depth-Control Technology
In addition to mechanical depth control, a more advanced method uses electrical detection. The drilling system detects electrical continuity through a copper layer and stops automatically when the specified layer is reached. This method can achieve zero-stub depth control, but it requires more specialized equipment and is intended for extremely high-speed PCBs, such as applications operating at 112 Gbps and above.
Back-Drill Diameter and Spacing Design
Back-drill diameter and spacing must be defined together with the via structure, neighboring copper features, and stackup. The back-drill must be large enough to remove the unwanted plated barrel, but it must also maintain adequate clearance from adjacent traces, planes, and vias. The exact values depend on the PCB design rules and manufacturing capability.
Methods for Measuring Via-Stub Length
Stub-length inspection is an essential part of closed-loop back-drilling process control. Three commonly used methods are described below.
1. Metallographic Cross-Sectioning
Principle: The PCB sample is cut through the center of the back-drilled hole. After resin encapsulation, grinding, and polishing, the remaining stub height is measured directly under a metallurgical microscope.
- Advantage: Direct and accurate measurement; it is considered the reference method for stub-length measurement.
- Limitation: The test is destructive and can only be performed on sampled boards, so it is not suitable for complete inspection of every board.
This method is suitable for first-article verification, process-capability evaluation, and failure analysis. The stated measurement accuracy can reach ±5 μm.
2. TDR Testing
Principle: A fast-rise-time pulse is transmitted through the PCB transmission line. When the signal encounters the impedance discontinuity created by a residual stub, part of the signal is reflected. By measuring the time delay of the reflected signal, the position of the discontinuity can be located and the stub length can be estimated.
- Advantages: Nondestructive, fast, visually interpretable, and capable of locating the discontinuity.
- Limitation: Specialized equipment and test fixtures are required.
TDR is suitable for batch or online inspection and for verifying impedance consistency. The referenced standards are IPC-2141A and IPC-TM-650 2.5.5.7.
3. Vector Network Analyzer Testing
Principle: A vector network analyzer measures S11, the reflection coefficient, and S21, the transmission coefficient. The residual stub length is then evaluated by analyzing the impedance response and transmission behavior.
According to the stated example, when the remaining stub exceeds 5 mil, or 0.127 mm, the S11 response increases significantly, with the value exceeding ?15 dB. A critical transition is also described at approximately 0.1 mm: S11 may deteriorate from ?22 dB to ?14 dB, exceeding a ?15 dB design threshold.
This behavior indicates that, for the server high-speed channels described, the stub may need to be controlled within 0.1 mm, or approximately 4 mil, to support signal-integrity requirements above 25 Gbps. For 112G PAM4 and other ultra-high-speed applications, the noise margin is particularly limited, so even a small stub-length deviation can reduce the eye opening, close the eye, and potentially cause packet loss. Some PCB manufacturers can consistently control residual stubs within 0.1 mm under suitable process conditions.
Conclusion
Controlling residual stubs in server PCB back-drilled vias is a system-level manufacturing task. A reliable process must form a complete control loop that begins with the design definition of the stackup and via geometry, continues through CCD positioning, Z-axis calibration, board-thickness compensation, drill-life management, and ends with verification using metallographic cross-sections, TDR, or network-analyzer measurements.
At 112 Gbps and higher, particularly in AI server and high-speed optical-module applications, a PCB is not merely a carrier for electrical connections. A dimensional difference of only 0.1 mm can substantially affect resonance, impedance discontinuity, reflection, and eye-diagram quality. For this reason, accurate back-drill depth control and appropriate stub-length testing are essential parts of high-speed PCB signal-integrity engineering.
