PTH Plated-Through-Hole Performance Metrics: The Hidden Lifeline of SMT Reliability

In modern SMT manufacturing, attention often centers on micrometer-scale solder paste printing accuracy, high-speed placement, and finely tuned reflow profiles. Yet when product reliability is on the line, a fundamental but easily overlooked physical characteristic inside the PCB often decides success or failure: the quality of the plated through hole (PTH).

As 5G, automotive electronics, and AI servers drive denser, thinner, and more multilayer PCB designs, the role of PTHs has expanded well beyond simple leaded component holes. They are the "highways" of interlayer interconnection, thermal conduction paths, and mechanical "bones" that carry cyclic thermomechanical stress. Industry analyses of SMT-line failures frequently trace roughly 30% of BGA soldering defects and 20% of through-hole component fractures back to PTH plating defects.

This article examines PTH performance metrics across Class 1 (general consumer) and Class 2 (high-reliability) expectations and explains why these parameters are critical to both PCB integrity and SMT process stability.

Part 1: Copper Thickness—From "Average" to the Minimum-Point Reality

Incoming quality control (IQC) at SMT factories often focuses on "average hole copper thickness." In actual product use, however, the local minimum copper thickness—the thinnest point along the plated hole wall—often determines long-term reliability.

1.1 Average Hole Copper Thickness

Typical requirements are:

• Class 2: ≥ 25 μm (984 μin)
• Class 1: ≥ 20 μm (787 μin)

SMT perspective: Average copper thickness drives overall current-carrying capacity. In high-current connectors or power devices, insufficient copper increases loop resistance, causes Joule heating under load, accelerates laminate aging, and can even lead to delamination or thermal damage.

1.2 Local Minimum Copper Thickness

The local minimum thickness (the thinnest point in the plated hole wall) is a decisive reliability parameter. Typical guidance is summarized below; see the appendix for a complete specification.

Why power boards require special treatment

Power boards experience large, periodic current pulses and intense thermal cycling. Because the Z-axis coefficient of thermal expansion (CTE) of FR-4 is much higher than X/Y, a thin, less ductile plated copper wall is prone to fatigue cracking after hundreds of thermal shock cycles. For power boards, such cracks can be precursors to catastrophic failures. Specifying a 25 μm local minimum copper thickness effectively buys lifetime insurance for the interconnect.

1.3 Special Considerations for POFV (Via-in-Pad)

For POFV (plated over filled via, via-in-pad) constructions, the plated hole wall must still meet the same thickness criteria even after filling. This is especially important under BGA pads: microcracks in the hole wall can propagate into the pad, creating latent opens or intermittent solder joints.

Part 2: Mechanical Properties Under Thermal Stress—Ductility and Throwing Power

If copper thickness is a quantitative measure, ductility and throwing power represent qualitative plating performance. These directly determine whether a PCB will survive the thermal stress of reflow soldering and service life thermal cycles.

2.1 Plated Copper Ductility: Prevent Brittle Fracture

Requirement: ≥ 18% elongation at room temperature (test method per IPC-TM-650 2.4.18.1).

• What is elongation? It is the strain copper can tolerate before fracture. Low elongation indicates a brittle deposit.
• SMT pain point: Peak reflow temperature reaches approximately 240–260 °C. FR-4 and copper have different CTEs. If the plated copper is not sufficiently ductile, the shear stress from laminate expansion can crack the hole wall. Products may test OK at the factory but fail after rework or extended field use—brittle copper fractures under thermal stress.

2.2 PTH Throwing Power: Meeting High Aspect Ratio Challenges

Typical requirements:

• Class 2: ≥ 70%
• Class 1: ≥ 60%

• Definition: Throwing power is the ratio of copper thickness at the hole center to the copper thickness on the board surface, expressed as (hole center thickness / surface thickness) × 100%.
• Process difficulty: As boards get thicker and holes get smaller (higher aspect ratio), it becomes increasingly difficult to achieve uniform plating in the hole center, where agitation and ion exchange are least effective.
• SMT linkage: Poor throwing power yields an ultrathin copper layer at the hole center. X-ray often shows these regions as darker areas. Such vias are prone to wall cracking during wave or reflow soldering, causing opens. Achieving 70% throwing power is a stringent test of bath chemistry control and equipment capability.

Part 3: The HDI Front Line—Blind and Buried Vias

In HDI designs, the quality of mechanically drilled buried/blind vias and laser-drilled microvias directly governs interconnect reliability.

3.1 Mechanically Drilled Buried/Blind Vias

• Requirement: Local minimum copper thickness: Class 2 ≥ 18 μm, Class 1 ≥ 15 μm.
• Explanation: Mechanical drilling can produce higher wall roughness due to tool vibration and resin smear. A thicker copper deposit helps cover micro-roughness and maintains signal quality.

3.2 Laser Blind Vias (Microvias)

• Requirement: Local minimum copper thickness: ≥ 12 μm.
• Explanation: Laser microvias are typically conical (wider at the top). Current density at the via bottom is lower during plating, making the bottom more susceptible to thin copper. The 12 μm target balances reliable interconnection against overplating that could complicate via filling. For very small passives (0201, 01005) and dense BGA routing, inadequate microvia copper can cause impedance discontinuities and degrade signal integrity.

Part 4: POFV Is Critical for BGA Soldering Yield

POFV (plated over filled via) is standard practice in high-density packages such as BGA and QFN. It eliminates via capture pad real estate and enables escape routing but introduces its own process controls that must be met to ensure SMT yield.

4.1 Wrap Copper Thickness

• Requirement: Class 2 ≥ 12 μm, Class 1 ≥ 5 μm.
• Role: "Wrap copper" is the copper that plates over the filled via resin. It must be thick enough to resist resin expansion during multiple reflow cycles. If too thin, the resin can push through, causing pad lifting and pad crater defects.

4.2 Copper Thickness at the POFV Surface (Via Top)

• Requirement: ≥ 6 μm (236 μin).
• SMT process window: While seemingly small, this minimum matters. If the copper on the filled-via surface is too thin, solder mask can bleed into the via during coating, creating pad planarity issues. In BGA ball attach or reflow, insufficient copper also reduces pad metallurgical strength and increases the risk of head-in-pillow (HIP) defects.

4.3 POFV Dish (Recess) Depth

• Requirement: ≤ 76 μm (2,992 μin).
• Practical note: When the "dish-down" recess is too deep, part of the printed solder paste fills the recess rather than forming the intended solder volume on the pad. If the recess approaches the upper limit, stencil design compensation—such as step stencils or larger apertures—may be necessary to ensure sufficient solder volume at BGA joints.

Part 5: PTH Wall Roughness and Visual Quality—Details Matter

5.1 PTH Hole Wall Roughness

• Requirement: ≤ 30 μm (1.181 μin), measured relative to the resin surface.
• Why it matters:
  • Signal loss: For high-speed channels (PCIe 5.0, 56G SerDes), rough copper increases conductor loss due to skin effect and can worsen insertion loss variability between vias.
  • Residue traps: Rough walls can trap etchants or micro-etch residues. Under heat and humidity, residues increase electrochemical migration (ECM) risk and may cause conductive anodic filament (CAF) or via-to-via shorts.
  • Stress concentration: Peaks and sharp features on a rough surface concentrate stress and can initiate copper wall cracking under thermal cycling.

Part 6: SMT-Focused PCB Quality Control Actions

Based on the above, the following quality control measures help translate PCB intrinsic quality into stable SMT yield.

1. Upgrade IQC inspection criteria:
   • Do not rely solely on "average hole copper thickness" certificates.
   • Request plated through hole microsection reports and review the local minimum thickness at both the hole entry and hole center.
   • For power boards, enforce a ≥ 25 μm local minimum copper thickness.
2. Establish material criticality classes:
   • Classify PCBs as "critical" vs. "general."
   • For critical applications (e.g., automotive, medical), require copper elongation data to verify ≥ 18% and avoid brittle deposits.
3. Optimize SMT process parameters:
   • Stencil design: Create a compensation matrix that links POFV dish depth to stencil step thickness and/or aperture enlargement.
   • Reflow profile: For thick or high-layer-count boards, lengthen the soak region to reduce thermal shock gradients and mitigate via wall stress.
4. Strengthen supplier audits:
   • Assess the PCB manufacturer's throwing power controls (e.g., solution agitation, vibration plating, horizontal plating capability, bath chemistry management).
   • Review the frequency and method used to monitor via wall roughness.

Conclusion: Reliability Is Engineered—and Controlled

PTH performance metrics may look like manufacturing-side numbers, but they are foundational to SMT process robustness. As system-level reliability competition increasingly shifts from silicon to packaging and interconnects, engineering teams must read the "microstructure language" of the PCB to predict risks and close process windows.

Only by integrating PCB intrinsic quality with SMT process capability can products deliver long-term reliability under real-world thermal and mechanical stress. For detailed PTH performance criteria, see the appendix below.

Note: Test methods referenced herein follow applicable IPC standards.

Appendix: PTH Performance Metrics