This article presents three design of experiments (DOE) case studies focused on wave soldering. The goal is to identify the dominant factors that drive solderability and defect rates, and to translate those findings into actionable PCB design guidelines and process settings for higher first-pass yield. The three topics are:
- PTH thermal relief and SMD-to-PTH spacing
- Wave solder and touch-up: reducing shorts, insufficient solder, and excess solder
- Spoke-style thermal relief pad design
PTH Thermal Relief and SMD-to-PTH Spacing DOE
Objective
Improve PTH solder fill rate by identifying significant factors affecting solderability. The study evaluates both the carrier tooling configuration for capacitors and the PCB design parameters to quantify their impact on wave solder fill.
Scope and Factors
Primary experiment:
A six-factor, three-level full factorial design was run across:
- Surface finish
- PTH clearance
- Annular ring width
- Carrier aperture size
- Carrier aperture angle
- Total connected copper cross-sectional area (contact area) tied to the PTH
Secondary experiments:
- Effect of connection layer location relative to the wave
- Impact of new routing schemes on solderability
- Effect of different total copper cross-sectional areas connected to the PTH
Expected Outcomes
- Determine the significant factors and optimal parameter ranges for solderability as a function of surface finish and copper cross section; provide design guidance to R&D and process engineering.
- Define the current production limit for PTH solderability as a function of total copper cross section connected to the hole.
Results and Analysis — Primary Experiment
- The dominant contributors to PTH solderability were:
- Contact area (total connected copper cross section)
- PTH clearance
- Carrier aperture size
- PTH clearance strongly affected solder fill. A unified design guideline of 11 mil per side is recommended.
- Carrier aperture size was positively correlated with solder fill. Contact area was inversely correlated: as more copper is tied to the PTH, solder fill decreased.
Based on 75% and 50% process targets, the experimental samples were treated as normally distributed and DPPM estimates were derived for different carrier aperture and angle combinations:
Results and Analysis — Secondary Experiments
- From the relationship between contact area and solder fill, when the connected cross section increased from 816 mil^2 to 912 mil^2, average solder fill dropped from 92% to 60%. Therefore, 816 mil^2 is the current equipment limit for meeting the target in this setup.
- Connecting layers facing the wave side exhibited higher solder fill, with an average improvement of approximately 15%. ANOVA main effects indicated statistical significance.
- Via-style connections soldered better than alternatives, with an average improvement of approximately 40%. ANOVA main effects indicated statistical significance.
DOE Summary and Design Guidance
- To achieve at least 50% solder fill on PTHs connected to large copper areas, reserve SMD-to-PTH spacing based on the total copper cross-sectional area connected to the PTH (contact area).
- Preset pad design conditions used for guideline derivation:
- PTH clearance: 11 mil per side
- Annular ring width: 9 or 13 mil
- Trace width: 8 mil
- Determine SMD-to-PTH spacing using a 3σ (standard deviation) basis relative to the expected variation in connected copper area.
Wave Solder and Touch-Up: DOE to Reduce Shorts, Insufficient Solder, and Excess Solder
Background and Objectives
- An MB lot rejection rate reached 18%, largely due to cosmetic residues and solder beads/slag on PCBA, far exceeding the 10% annual target. The focus was to reduce defects attributable to wave solder (W/S) and hand-solder touch-up (T/U) to improve first-pass yield (FPY).
- Conduct a DOE to optimize wave solder process parameters: flux deposition, preheat temperature, conveyor incline angle, and solder contact (dwell) time.
- Meet customer expectations for improved solder quality.
S/N Ratio (Smaller-the-Better) for Shorts, Insufficient Solder, Excess Solder
- Optimal parameter combination:
- Flux deposition: 1400 μg/in^2
- Preheat temperature: 115 °C
- Conveyor incline angle: 5°
- Solder contact time: 8 s
- The conveyor incline angle was the most significant factor influencing DPPM.
Variance and Contribution Analysis
- Significant contributors to DPPM (from variance analysis): conveyor incline angle and preheat temperature.
- Contribution rates: conveyor incline angle 61.3%, preheat temperature 19.7%.
Response Surface Analysis
- Predicted optimum region: when the conveyor incline angle is below 5° and preheat temperature is between 100–120 °C, the modeled DPPM is approximately 1518.
- Practical interpretation:
- For overall DPPM, preheat must reach the flux supplier’s recommended activation temperature to properly clean copper surfaces. Excessive preheat can be detrimental for low-solids no-clean fluxes.
- Smaller conveyor incline increases the PCB’s contact area and thermal input in the solder wave, improving wetting and mitigating insufficient solder conditions.
DOE Summary
- S/N analysis (smaller-the-better):
- Optimal process settings: flux 1400 μg/in^2, preheat 115 °C, conveyor incline 5°, contact time 8 s.
- Most significant factor: conveyor incline angle.
- Variance analysis:
- Significant factors: conveyor incline angle and preheat temperature.
- Contributions: angle 61.3%, preheat 19.7%.
- Response surface:
- Angle below 5° and preheat 100–120 °C projects DPPM below approximately 1518.
Spoke-Style Thermal Relief Pad Design DOE
Full Factorial Design
Seven factors that affect PTH solder fill were selected: four PCB design parameters, one material parameter, and two process parameters.
Correlation Analysis: Minimum vs. Average Solder Height
- Production inspection uses the minimum solder height per pin, while this DOE primarily analyzed average solder height as a proxy for solderability. A correlation study was conducted to validate whether average height can represent the minimum criterion.
- The linear correlation coefficient between minimum and average solder height was 0.97 with P < 0.05, indicating a strong positive correlation. Therefore, average solder height is an effective measure for variance analysis in this context, and the measured averages are representative of overall solderability.
These three DOEs quantify how connected copper area, thermal relief design, and wave solder process parameters jointly determine PTH solderability and defect rates. The resulting design guidelines (e.g., PTH clearance and SMD-to-PTH spacing versus connected copper area) and optimized process window (flux, preheat, conveyor angle, contact time) provide practical knobs to improve first-pass yield without trial-and-error.
