On a 4-layer PCB, trace width and spacing decisions set both the current capacity and the impedance before you finish the first net. Outer layers are microstrip over the nearest plane. Inner layers, when used for signals, sit between planes and behave more like stripline. The same copper weight does not give the same finished width or the same thermal margin on both. Most problems start when the designer picks a width for current or impedance on one layer and copies it to the other without checking the stackup or the fab process.
Four-layer boards typically run 1 oz on the outer layers and 0.5 oz or 1 oz on the inners. That difference changes both the etch undercut and the current the trace can carry for a given temperature rise.
Current Capacity, Copper Weight, and Temperature Rise
IPC-2221 still governs most current-capacity checks. The external-layer constant is roughly twice the internal-layer constant because outer traces can lose heat to air. For 1 oz copper and a 10 °C rise, a 1 A trace needs about 12 mil on an outer layer and roughly 30 mil on an inner layer. A 3 A outer trace lands near 54 mil; the same current on an inner layer needs more than 100 mil. Accepting a 20 °C rise cuts those widths, but many designs stay at 10 °C for margin.
Copper weight scales the cross-section. 2 oz outer copper roughly halves the width needed for the same current. The catch is etch undercut. Thicker copper needs more etch time, so the finished width is narrower than the artwork and the minimum space the fab will guarantee increases. A 2 oz outer design that worked at 6 mil space on 1 oz often needs 8 mil or more to hold yield.
Signal Spacing for Crosstalk and Isolation
On outer-layer microstrip the 3W rule (center-to-center spacing equal to three times the trace width) keeps most moderate-speed digital crosstalk acceptable. Clocks and multi-gigabit pairs usually need 5W or greater, or they should sit on opposite sides of the ground plane. Parallel length multiplies the coupling; a short run at tighter spacing often causes less trouble than a long run at the minimum. Inner-layer stripline, when the stackup allows it, couples less because the field is contained between planes, but a standard 4-layer board rarely has true stripline signal layers.
Voltage clearance is separate from crosstalk. Below 30 V, 4–5 mil space is usually enough on standard FR-4. Above 50 V open the gap further even if the fab can etch tighter. Soldermask is not a reliable dielectric barrier for high-voltage isolation.
Impedance Control and the Width–Height Relationship
Characteristic impedance depends on trace width, copper thickness, and the dielectric height to the reference plane. On a typical 4-layer stackup with 4–5 mil core to the ground plane, a 50 Ω single-ended microstrip often lands in the 8–12 mil width range for 1 oz copper. Thinner dielectric forces a narrower trace for the same impedance; thicker dielectric allows a wider one. Finished copper thickness also shifts the number—plating adds thickness on outer layers and lowers impedance slightly for a given width.
Copying a width from one stackup to another fails. The dielectric constant, soldermask on outer layers, and exact prepreg thickness all move the result. Calculate for the production stackup and confirm with the fabricator's impedance coupon. Differential pairs follow the same logic: width and intra-pair gap set the differential impedance once the height is fixed.
Outer-Layer Versus Inner-Layer Trace Behavior
Outer layers see plating, so finished copper is thicker than the base foil. They also etch from one side in a more aggressive environment, which increases undercut and raises the practical minimum width and space. Inner layers etch more uniformly and can often hold tighter geometries for the same copper weight. Electrically, outer traces are microstrip with part of the field in air; they propagate faster and radiate more than a buried trace. On a standard 4-layer board the inner layers are usually the ground and power planes, so most signal routing stays on the outer layers where these effects dominate.
When an inner signal layer is present, the reference distance is usually larger and the impedance calculation switches to a stripline model. Do not reuse outer-layer widths on that layer.
Power Traces Versus Signal Traces
Signal traces are sized for impedance or for low current. Power traces are sized for current and voltage drop. A 2 A power trace on 1 oz outer copper needs roughly 30 mil for a 10 °C rise; the same net as a signal line might be 5–8 mil. Long power runs also need a voltage-drop check—resistance scales with length and inverse cross-section. Pour copper or use planes for high-current distribution instead of long wide traces when possible. Keep high-current traces away from sensitive analog or high-speed nets; the magnetic field around them couples.
Manufacturing Limits on Minimum Width and Space
Most standard FR-4 fabs quote 4/4 mil or 5/5 mil as the reliable floor for 1 oz copper. Inner layers can sometimes go to 3.5 mil with LDI and controlled etching. Move to 2 oz and the practical outer-layer minimum rises to 6–8 mil because of undercut and residual copper risk. Designing at the absolute minimum raises cost and scrap rate. A 6/6 mil rule is the common sweet spot for cost and yield on ordinary 4-layer boards. Tighter geometries move the job into a premium process with longer lead time and lower yield.
Finished width is always smaller than the artwork because of etch undercut. Compensate in the design or confirm the fab's compensation practice before locking the impedance target.
Balancing Electrical Needs Against Process Capability
Start with the current or impedance requirement, then check whether the resulting width and space fit the copper weight and the fab's standard process. If a high-current net forces a wide trace that crowds adjacent signals, move the current to a plane or increase copper weight rather than squeezing the space. If impedance forces a narrow trace on thick copper, consider a thinner dielectric or a different layer. On a 4-layer PCB, a trace width and spacing choice that ignores either the electrical target or the etch physics ends up as either a reliability problem or a yield problem. Confirm both with the stackup calculator and the fabricator's capability chart before releasing the Gerbers.
