The usual file that lands in review has "50 Ω" on the drawing and 0.20 mm traces on a 1.6 mm two-layer stack. Or the opposite: a PCIe pair routed like GPIO because the last board "just worked." Same mistake. FR4 PCB controlled impedance is not a checkbox for a board that feels fast. It is a stackup and etch commitment you take when the trace starts acting like a transmission line.
If the edge settles before the reflection comes back, impedance is a courtesy. If that reflection lands in the receiver window, it is the design.
Controlled Impedance Is a Geometry, Not a Net Name
Target Z0 is L and C per unit length on that stack. Width, copper thickness, dielectric height to the reference, Dk, soldermask on microstrip, gap on a differential pair. Change any one after layout and the schematic number is fiction.
CAD calculators assume uniform dielectric and a solid reference. FR4 is glass and resin. The calculator is a starting point. The coupon is the contract. IPC-2141 is close enough at USB / HDMI / GbE rates. It does not replace a locked stackup note: copper weight, finished thickness, masked microstrip or buried stripline.
When a Trace Becomes a Transmission Line on FR4
Treat the net as a line when its length is longer than about one-sixth to one-tenth of the flight distance that fits inside the rise time. Outer FR4 microstrip is roughly 140–160 ps/inch. A 1 ns edge already makes a 2–3 inch run interesting. A 200 ps edge makes a connector escape interesting.
Clock frequency is not edge rate. A 25 MHz clock with a 300 ps driver is a fast edge on a long stub. I2C at 400 kHz on a 40 mm run is not. Same laminate. Different problem.
Return path is part of the line. A 50 Ω width over a split plane is not 50 Ω. If you specified controlled impedance FR4 and then cut the reference to sneak a pour through, you cancelled the spec.
Signals that actually need a target Z0
Single-ended 50 Ω: RF drops, some ADC/DAC analog, clocks that leave the board, SMA / U.FL launches. USB 2.0 high-speed is 90 Ω differential. Label it 50 and CAM etches the wrong width.
Differential that shows up every week: USB 2.0 / 3.x (90 Ω), HDMI / DP (100 Ω), PCIe (85–100 Ω per the spec note), SATA, Ethernet 100 Ω, MIPI, LVDS, DDR. DDR is impedance plus length matching. Matching on a wrong Z0 just makes a clean wrong wave.
No coupon needed: reset, LED, fan tach, 400 kHz I2C, GPIO, bulk power. EMC can still care about those edges. That is filtering and return path, not a ±10% impedance class.
Why a 1.6 mm Two-Layer Stack Fails the 50 Ω Conversation
On 1.6 mm FR4 with ground on the far side, 50 Ω wants something near 2.5–3.5 mm wide at 1 oz. That is a pour, not a signal. The 0.15–0.20 mm traces everyone routes on that stack sit closer to 90–120 Ω. Calling them controlled impedance does not change the physics.
Two-layer is cheaper. Placement is done. USB or Ethernet lands last and someone types "90 Ω diff" in the fab notes. The factory can etch the width you drew. They cannot invent a dielectric height you did not buy.
Four-layer with 0.10–0.20 mm prepreg L1 to L2 is the normal FR4 answer. 50 Ω single-ended lands around 0.12–0.20 mm depending on copper and mask. 90–100 Ω differential is width plus gap. Lock that stack before connector fanout. Changing prepreg after routing to hit Z0 moves via aspect, plane capacitance, and the thickness note in one ECO.
Commodity FR4 Dk is not 4.5 at every frequency. Resin content, glass style, and the 1 MHz datasheet number used at 5 GHz all shift it. Standard FR4 still ships USB3 and PCIe Gen3 every day. It is the wrong laminate for a long 10G run if the eye is already thin. That is a material call, not a wider trace.
What Fab Actually Controls When You Ask for a Target Impedance
The factory does not "set impedance." They etch a compensated width on a stack they already build, then measure a coupon. Typical commercial class on FR4 is ±10%. Tighter than ±8% is a process conversation. ±5% on masked outer microstrip is where quotes get honest and go up.
Soldermask on microstrip lowers Z0 a few ohms. Calculator assumed bare copper, coupon reads low. 0.5 oz and 1 oz do not share a width — finish copper is thicker than foil, and the wall is a trapezoid. CAM offsets the artwork. "Do not touch my widths" plus "90 Ω" is two notes that fight.
Glass weave is the quiet miss. A narrow pair on a resin channel next to a 7628 bundle sees local Dk swing that length matching never sees. The coupon is a fat test structure. It will not catch weave under your 0.10 mm lines.
List each class on the drawing: 50 Ω SE, 90 Ω diff, 100 Ω diff. Layer, reference, finished copper, masked or not, tolerance. "Impedance control required" with no table ships as standard etch. Give a stack you will accept, or take the house stack that hits those numbers. Prototype on 0.08 mm prepreg and production on 0.18 mm is a silent Z0 shift. Widths stay. Dielectric does not.
What Breaks When the Spec Is Wrong or the Stack Is Late
Reflections first. Overshoot. A shelf in the edge. USB that enumerates on a short cable and drops on a long one. HDMI that sparkles on one sink. DDR that trains cold and loses an eye when the driver impedance moves with temperature.
Then EMI. A pair sitting at 120 Ω on a 90 Ω interface radiates more of the odd mode you already had from a via stub. Tight Z0 plus 1 oz plus a fine gap on cheap FR4 is etch-limited — coupon fails, widths get biased, mask dams disappear. Specify what the interface needs. Do not put ±5% on a 400 kHz net because the title block had an impedance section.
What to Decide Before the First Fanout
List the interfaces that leave the board or run farther than a rise-time fraction. Put a real Z0 and a real stack next to each one. Two-layer plus those interfaces means change layer count or stop calling it controlled impedance.
Keep the reference solid. No splits under the pair. No reference change without a via fence. Match lengths after the geometry is frozen. Ask for a coupon on the classes you named. Read it against the drawing, not last month's calculator screenshot.
You need FR4 PCB controlled impedance when the edge and the length say the trace is a line, and when the interface spec wrote a number. You do not need it on every net that shares the laminate. Lock the stack. Then route to that stack. Everything else is a note the etcher cannot honor.
