Getting started with PCB layout is not hard. Falling into avoidable traps is. Many people finish the flow from schematic import to Gerber output and assume they can design boards. The boards that come back then whistle, pick up interference, or, in serious cases, destroy parts as soon as power is applied.
Looked at after the fact, most of these problems come from elementary mistakes. The mistakes themselves are not hard to understand. They are just easy to overlook. The ten below are worth checking against your own work.
1. Starting layout with default DRC rules
Many beginners open the tool and start routing with default DRC values. Trace width, clearance, and via size are left untouched. Default rules are meant for the simplest boards. Slightly more complex designs cannot survive them. Insufficient trace width limits current-carrying capacity. Clearance that is too tight may be unmanufacturable. Vias that are too large waste routing space.
The correct approach is to calculate trace width from board thickness, copper weight, and current demand before routing, and to set minimum clearance and minimum width from process capability. DRC is a safety net. If you never set the floor, problems are only a matter of time.
2. Right-angle and acute-angle traces
This is probably the most classic beginner mistake. A right-angle corner changes trace width abruptly. A high-speed signal passing through that corner sees an impedance discontinuity, and reflection follows. Acute angles are worse. The impedance problem is more severe, and acid traps can over-etch the copper, lowering yield.
Use 45-degree bends or arc transitions. That is simple to say, but once density rises and a deadline is close, pulling a right angle by habit is common. After routing, search the board for right angles. Use the tool's check function rather than hunting by eye.
3. Decoupling capacitors placed far from the pins
A decoupling capacitor supplies transient current to an IC. Closer is better. Many beginners place capacitors in a neat ring around the IC, then route a long path before the connection lands. Equivalent inductance rises quickly, and the capacitor becomes ineffective.
The farther a decoupling capacitor is from the pin, the faster high-frequency decoupling falls off. Within 5 mm is still workable. Beyond 10 mm it is largely decoration. Some beginners put all capacitors on the board edge because it looks tidy. That provides essentially no decoupling. Place capacitors as close to the IC pins as possible, keep the traces short and wide, and put vias next to the pads.
4. Chopping the ground plane into fragments
The ground plane is one of the most valuable resources on a PCB. A continuous ground plane provides the lowest return-path impedance and is critical for EMC and signal integrity. Beginners often pay little attention while routing. Signals cross at will, vias are dropped at will, and a continuous ground layer is cut into islands.
Once the plane is split, return current must detour. The resulting loop area acts as an antenna. Radiated emissions rise, crosstalk increases, and problems follow one after another. Do not route signals on the ground layer if it can be avoided. If it cannot be avoided, do not cut the plane into islands.
5. Critical signals crossing a split plane
This item is tightly tied to the previous one. When a high-speed trace crosses a gap in the ground plane, the return path is forced around the split and forms a large signal loop. That loop radiates and is also easy to couple with external noise.
For clocks, differential pairs, and high-speed buses, the reference plane directly underneath must be continuous. If a split cannot be avoided, reroute around it or place stitching capacitors at the crossing to give return current a path.
6. No length matching on high-speed signals
High-speed interfaces such as DDR, PCIe, and USB 3.0 require tight consistency in arrival time. If a differential pair or a bus group differs too much in length, signals arrive at the receiver at different times. Timing margin is consumed. Bit error rate rises, or communication fails outright.
Length matching is not finished by drawing a serpentine. Spacing, amplitude, and coupled length of the serpentine all matter. Spacing that is too small adds extra crosstalk. Amplitude that is too large wastes routing space. Set the parameters from signal rate and protocol requirements. Do not draw by feel.
7. Power traces too thin for the current
On 1 oz copper, a 1 mm trace width can carry about 1 A. Many beginners have no sense of that number. Power traces drawn as thin as signal traces become heating elements when the board is powered. Voltage drop can starve the chip. In worse cases the copper burns open.
Power-trace width must be calculated from actual current, with margin. Use wide traces or copper pours on high-current paths. Where needed, add thermal pads and via arrays at the pads to help heat spreading and current sharing.
8. Silkscreen covering pads
Silkscreen on a pad looks minor. The effect is not. Ink on the pad reduces solderability and can cause poor joints or insufficient wetting. Some fabricators delete pad silkscreen before shipment. Not every factory does that step.
Before generating Gerbers, check overlap between the silkscreen layer and the pad layer. Most EDA tools provide this check. Build the habit. Do not leave this class of problem for the fabricator to clean up.
9. Vias placed in pads
Dropping a via directly in a pad during BGA fan-out does appear on very dense boards. Beginners often do it to save effort. A via in a pad lets solder drain through the hole and leaves the joint starved, especially in wave solder, where the problem is almost guaranteed.
If a via-in-pad is truly required, use resin plug and cap plating. That adds manufacturing cost. When it is not necessary, place the via beside the pad and connect with a short trace.
10. No test points on the board
The layout is finished. Every signal has a path. Nothing looks wrong. During debug there is nowhere to put a probe on a critical net: the pad is too small, parts block access, or the only option is a flying wire.
Test points are not optional decoration. Critical power nodes, clocks, reset, and debug interfaces need test pads or test vias during layout. A few test points do not add cost and can save a large amount of debug time. A board with no test points makes debug far harder than it needs to be.
Making a mistake once is useful. Repeating it is not
Almost everyone who layouts boards has made at least half of these ten mistakes. The difference is that some people remember after one occurrence, while others repeat the same trap on every board. In PCB design, experience is valuable because a trap that has already been hit need not be hit again, provided you know where the trap is.
