Most high-power packages on FR4 fail thermally for the same reason: the designer treats the thermal pad as a copper island instead of the start of a controlled heat path. The junction-to-board thermal resistance stays high, the copper immediately under the package saturates, and the rest of the board never sees the heat. Thermal vias are the only practical way to break that bottleneck on standard FR4.
The following notes come from repeated DFM reviews of power stages, motor drivers, and LED drivers where the thermal via array looked adequate on the layout screen but failed once the board hit real current and ambient.
How Heat Actually Leaves the Package on FR4
FR4 itself is a poor conductor—roughly 0.3 W/m·K through the thickness. Copper is three orders of magnitude better. The only low-resistance path is therefore copper-to-copper: die attach → package thermal pad → PCB top copper → plated vias → internal plane or bottom copper → eventual heatsink or chassis.
If the vias stop at the first internal plane and that plane is not continuous or is cut by routing channels, the heat simply stops. Many layouts show a dense via array under the pad that then dead-ends into a fragmented ground pour. The measured board temperature rise is then almost the same as a board with no vias at all.
The critical first decision is therefore not the via count. It is whether a continuous copper path exists from the package thermal pad all the way to the final heat-spreading surface.
Thermal Via Count: Enough to Drop Resistance, Not Just Fill the Pad
A single 0.3 mm finished-hole via with 25 µm average plating carries roughly 50–80 °C/W thermal resistance for a 1.6 mm board thickness. That number is high enough that one or two vias under a 5–10 W package do almost nothing.
Practical minimums observed across power MOSFET, DPAK, and power QFN footprints:
- 3–5 W continuous: 9–12 vias
- 8–15 W continuous: 16–25 vias
- 20 W+ or pulsed high peak: 30+ vias or move to a metal-core substrate
The vias must sit inside the thermal pad copper, not around it. Vias placed in the solder-mask-defined clearance or outside the pad add almost no value because the heat still has to travel laterally through thin top copper first.
Over-populating the pad with vias is also common. Once the via array thermal resistance drops below the package's own θJC, additional vias return diminishing returns and start to hurt solder joint reliability by reducing the continuous copper area available for wetting.
Via Pitch and Drill Density Limits That Matter in Production
Pitch is where layout intent collides with the drill shop. A 0.8 mm pitch array looks dense and "thermal" on the CAD screen. In production it produces three recurring problems:
Drill wander and broken bits rise sharply below 1.0 mm pitch on standard FR4. Aspect-ratio plating becomes uneven; the vias near the center of a dense cluster often show thinner copper than the edge vias. That variation shows up later as localized hot spots.
Recommended working range for 0.3 mm drill on 1.6 mm FR4:
- Minimum center-to-center pitch: 1.0 mm
- Preferred pitch for reliable plating: 1.2–1.5 mm
If the thermal pad is small, accept fewer vias at correct pitch rather than force a dense array that the fabricator will flag or that will plate inconsistently. Some shops will accept 0.9 mm pitch with laser-drilled microvias, but that is a different cost and process stack.
Copper Plane Continuity Under the Via Array
The vias are only as good as the copper they land on. A common failure mode is a solid top thermal pad connected by vias to an internal plane that is then cut into islands by signal routing or split planes. Heat reaches the first plane and stops.
Best practice observed on boards that actually stay within temperature limits:
- Keep at least one full internal plane (usually GND or power) continuous under the entire via array and extending at least 10–15 mm beyond the package outline in every direction.
- Connect the vias to that plane with full annular rings—no thermal reliefs on the plane side.
- If a bottom-side heatsink or chassis contact is planned, bring the vias all the way through and pour solid copper on the bottom under the component footprint.
Thermal reliefs on the top pad are sometimes still required for solderability on large copper areas, but they should be minimal spoke designs so they do not choke the lateral heat flow into the vias.
Practical Thermal Resistance Targets and Layout Adjustments
Rough order-of-magnitude check used during layout review: target the via array contribution to board-level θJA below 3–4 °C/W for packages dissipating more than 8 W continuous. That usually means 16–20 properly plated vias into a continuous plane on 1.6 mm FR4 with 2 oz outer copper.
If the calculated or measured rise is still too high after maximizing via count and plane continuity, the next levers are:
- Increase outer copper weight to 2 oz or 3 oz under the power stage.
- Add a second via array outside the package that couples the top copper pour into the same internal plane.
- Move to a 4-layer or 6-layer stack with two full power/ground planes rather than trying to force everything through a 2-layer board.
FR4 glass-transition temperature remains the hard limit. Even with perfect vias, local board temperature above ~130–140 °C under continuous load will eventually cause resin softening and via barrel cracking. At that point the correct fix is either a different laminate or an external heatsink, not more vias.
The layouts that pass thermal validation are the ones where the designer treated the via array as a thermal conductor with defined resistance, pitch constraints, and plane continuity requirements—exactly the same way signal vias are treated for impedance. Everything else is decoration that disappears under load.
