A via on a PCB may be connected only to a signal, while an internal power plane has no net assigned to it. Yet during CAM inspection, the copper around the via may appear dangerously close to the hole, or even show a localized unintended connection. The problem is often not the netlist, but the anti-pad in the pad stack. The anti-pad determines how much clearance the non-target plane must maintain around the via. If only the drill and surface pad are defined, or if the anti-pad is copied as an undersized fixed value, there is no room to absorb manufacturing tolerances.
An Anti-Pad Is More Than Empty Space
A through-hole pad stack should at least distinguish among the drill, regular pad, thermal pad, and anti-pad. The regular pad provides the connection to the target signal layer or positive plane layer. The thermal pad determines how many spokes connect the plane to the pad. The anti-pad is used on plane layers that should not connect, pulling copper back from around the hole and pad. Although it has no conductive function, it is the geometric definition that establishes the actual isolation relationship in the photolithography data. Negative plane layers are particularly easy to misinterpret: the circular shape shown in the editor may represent an area to be removed after output rather than additional copper.
Anti-Pad Size Cannot Be Determined by Simply Adding to the Drill Diameter
The anti-pad boundary must account for the finished hole diameter, hole-wall copper, drill wander, layer-to-layer registration, and the required electrical clearance. If only a small fixed increment is added outside the drill, the remaining copper clearance can quickly disappear as the hole diameter increases, the number of PCB layers increases, or the fabricator's capabilities change. On the other hand, making the anti-pad unnecessarily large can fragment the reference plane, narrow power paths, and increase plane discontinuity around high-speed vias. An appropriate value should be derived from the PCB fabricator's minimum hole-to-copper capability, pad stack type, network voltage, and return-current requirements, and then implemented in the design rules rather than treated as a universal number.
Distinguish Direct Connections from Thermal Connections on Target Planes
A via sharing a net with an internal plane does not mean that every connection method is appropriate. High-current paths or high-speed return paths may require a low-impedance direct connection, while through-hole components that must be soldered often require thermal relief pads; otherwise, a large copper plane can rapidly draw heat away during soldering. A non-target plane must use an anti-pad. If the same pad stack in a library incorrectly reuses Regular, Thermal, or Anti-pad definitions on different layers, one layer may fail to connect when it should, while another layer that should remain isolated may end up dangerously close. During review, inspect the connection result layer by layer rather than relying only on a 3D view or top-layer net highlighting.
Perform a Reverse Check After Generating Manufacturing Data
Hide the silkscreen and components and display only the drills, all plane layers, and the board outline. Highlight the target and non-target nets separately, looking for abnormal thin copper rings, plane islands, and overlapping clearances. Then open the final Gerber or ODB++ data and measure the distance from the hole wall to the copper edge at several minimum-clearance locations rather than measuring from the design drill center to the copper edge. BGA regions, densely populated connector vias, via fences, and power-plane split boundaries should be prioritized for sampling. If the library was imported from another EDA system, also verify that the anti-pad definition has not been lost during format conversion.
Treat the Pad Stack as Four Transparent Layers
When reviewing a critical via, export four layers at the same coordinates: the drill, regular pad, thermal pad, and anti-pad. First determine whether the layer should be connected, then verify which graphic definition is being applied. In library management, record the drill diameter, finished hole, surface pad, internal-layer pad, anti-pad, and solder mask opening separately. Changing any one dimension should trigger a complete review of the pad stack. If the PCB fabricator returns an enlarged clearance requirement, synchronize the change back to the library and design rules rather than accepting only a CAM compensation; otherwise, the same issue will recur in the next revision.
Functional pads must also be distinguished from non-functional pads. Some through-holes retain non-functional pads on internal layers where no electrical connection exists, while other manufacturing processes remove them. These choices affect local copper distribution, drill reliability, and plane clearance, so they should not be treated as the same concept as an anti-pad. If an anti-pad around a high-speed via is too large, the return path is forced to detour. Although parasitic capacitance may decrease, plane continuity can become worse. If the anti-pad is too small, capacitance and the risk of manufacturing shorts increase. Simulation, design rules, and manufacturing capabilities should all use the same pad-stack data.
For differential vias, also check that the anti-pads on both sides are symmetrical and that adjacent ground vias remain within continuous reference copper. If first-article cross-section analysis or flying-probe results show drill wander or insufficient copper clearance, trace the issue back to the library's design margin rather than attributing it solely to PCB fabrication variation.
When implementing the rules, through-holes, blind/buried vias, and backdrilled vias should also be managed separately. Backdrilling changes the stub and finished-hole structure, while plane-layer clearances must still account for drill wander and layer registration errors. The review record should document the applicable PCB fabricator capability revision, minimum anti-pad clearance, and sampled coordinates so that the requirements remain traceable when the fabricator or stackup changes. This prevents outdated rules from being applied to a new manufacturing process without review.
The acceptance criterion for an anti-pad is not simply that a ring of empty space appears in the PCB editor. In the final manufacturing data, every non-target plane should retain a clear, measurable, and explainable hole-to-copper clearance without unnecessarily fragmenting the reference plane.
Whether a via is safe depends on both the layers it should connect to and the layers it should remain isolated from. Does your current pad library list anti-pad dimensions as a separate item during footprint review?
