HDI Stackup Design Guide: 1+N+1, 2+N+2, and Any-Layer

HDI stackup design is the choice of build-up architecture that decides how microvias, buried vias, and the core are stacked so a board can escape fine-pitch parts without extra lamination cycles. Teams search this topic because HDI is treated as one product, while production treats those structures as different process families. The wrong call shows up later as fanout congestion, warpage, impedance drift, long lead time, or a quote that jumped because the via matrix was never reviewed.

This guide is written for that decision, not for a glossary. It covers notation, IPC types, what each structure can actually route, the rules that change yield, and a selection path you can use in a design review.

Highlights

• Treat 1+N+1, 2+N+2, and Any-layer HDI stackup as separate process families. Layer count alone does not define cost or capability.
• Start at the simplest structure that completes BGA escape and meets thickness, impedance, and reliability. Upgrade only when a trial route fails.
• Put both languages on the fab drawing: IPC type and i+N+i notation, plus via spans, fill, and VIP notes.

In the sections below you will decode stackup notation, compare sequential build-up with Any-layer construction, see which design rules actually move yield, and walk a selection framework before CAM.

What Is HDI Stackup Design?

HDI is a manufacturing method, not a marketing label. In process terms it means laser microvias, thinner build-up dielectrics, sequential lamination, and more interconnect per unit area than you get by adding conventional through-hole layers.

Designers often mix three different things:

1.  Total copper layer count

2.  Build-up architecture: 1+N+1 versus Any-layer

3.  Via architecture: blind, buried, stacked, staggered, skip, via-in-pad

The stackup is the HDI manufacturing contract. It tells the fabricator how many press cycles, laser steps, copper-fill steps, and registration events the panel needs. That contract is locked before detailed routing. Once you freeze the structure, you have also frozen microvia aspect ratio, whether the core can still use mechanical PTH, and whether buried vias are even available.

Conventional multilayer is still the better answer when pitch is coarse, pin density is low, and unit cost dominates. HDI becomes cheaper when it removes layers, shrinks the board, or shortens via stubs enough to recover the process premium. Jumping to Any-layer because a flagship phone uses it is not a design method.

HDI Stackup Notation: How to Read 1+N+1, 2+N+2, and i+N+i

The first number represents the build-up layers on the top side, while N refers to the core or inner sub-stack, and the last number indicates the build-up layers on the bottom side. When comparing an HDI 1+N+1 vs. 2+N+2 stackup, it is important to understand that this notation describes the board's process architecture rather than its total number of layers.

A common mistake is reading 1+N+1 as three layers. It is not.

Some manufacturers write M+bN+M when the core contains buried vias, for example 1+b8+1. Production boards usually keep equal build-up on both sides to control warpage. Asymmetric constructions exist, but they need explicit fab agreement. N is usually even for copper and mechanical balance. Confirm that with the shop rather than treating it as a law.

HDI Stackup Types: IPC-2226 vs. Fabricator Notation

You need both languages. IPC-2226 Types I–VI live on documentation and capability claims. i+N+i and Any-layer live on quotes and CAM.

The mapping is a range, not a 1:1 shop process:

• Type I / II ≈ 1+N+1. Type II adds buried vias in the core.
• Type III ≈ 2+N+2 and higher sequential build-up with stacked or staggered microvias.
• Types IV–VI / ELIC / ALI ≈ Any-layer HDI stackup.

Put both on the drawing: IPC type and 2+6+2, staggered or stacked, copper-filled VIP, buried via in core, and so on. "HDI, 10 layer" is not a specification.

HDI Stackup Types: 1+N+1, 2+N+2, 3+N+3, and Any-Layer

Each structure has a routing envelope and a process price. The useful question is not which is more advanced, but what fails first if we stay here.

1+N+1 HDI Stackup

One sequential build-up layer sits on each side of an N-layer core. Typical boards are 1+2+1, 1+4+1, 1+6+1, and 1+8+1.

Laser microvias run L1–L2 and Ln–Ln-1. The core often still uses mechanical PTH. Type II adds buried vias so the outer layers stay free for fine routing.

Process flow is short: laminate the core, add outer dielectric and foil, laser drill, plate. That is the lowest sequential-cycle count among true HDI.

In typical production microvia diameter is often 75–125 μm and outer line/space is 50–75 μm, depending on the fab. Comfortable BGA pitch is usually 0.4–0.5 mm. 0.4 mm is possible with via-in-pad and a planned fanout.

Strengths are lead time, yield, DFM, and the smallest cost premium versus conventional PCB. The limit is simple: one HDI routing layer per side. Dense 0.35 mm-class BGAs often run out of escape channels.

Typical uses are wearables, mid-density consumer boards, industrial modules, cost-sensitive IoT, and the first step up from a 6–8 layer through-hole design.

2+N+2 HDI Stackup

Two sequential build-up layers per side is the most common real high-density stackup in volume electronics. Typical constructions are 2+2+2, 2+4+2, 2+6+2, and 2+8+2.

This is where via strategy starts to matter. Staggered microvias offset lands from layer to layer. They are usually more robust in thermal cycling and easier for the fab. Stacked microvias form a vertical column. They save real estate under a BGA but need copper fill, planarization, and tighter process control. Stacking a microvia onto an unfilled mechanical buried via is a reliability risk unless the fabricator explicitly supports that joint.

Designers move here when 1+N+1 cannot finish 0.3–0.4 mm BGA escape, when high-speed pairs need cleaner referencing, or when an 8-layer 2+4+2 can replace a 10–12 layer conventional board. Typical production ranges are 60–100 μm microvias and 50–75 μm line/space, with 40–50 μm at capable shops. Cost rises because you added a lamination, laser, and fill cycle. Yield usually sits a step below 1+N+1, but the structure is still far more available than Any-layer.

2+N+2 is usually seen on compute modules, 5G radio boards, ADAS controllers, networking cards, and industrial cameras.

3+N+3 HDI Stackup

Treat 3+N+3 as the answer when 2+N+2 cannot finish fanout, not as the default next upgrade. Typical constructions are 3+4+3, 3+6+3, and 4+N+4 on extreme SoC or AI module boards.

The extra "i" buys more HDI signal layers, deeper stacked via columns, and a way to keep the finished board thin while adding routing planes. It also buys another press, laser, plate/fill, and registration event. Lead time, scrap risk, and material constraints all rise.

4+N+4 is not interchangeable with Any-layer. It still has a core. Any-layer is a different interconnect philosophy.

Any-layer HDI Stackup

An Any-layer HDI stackup allows laser microvias between any adjacent layers. With stacked filled vias, that becomes effective any-to-any routing.

The board is built by repeating thin-dielectric build-up, laser drill, copper-filled stacked microvias, and tight layer-to-layer registration. Mechanical PTH is reduced or removed. The structure exists for ultra-fine BGA/CSP, maximum wiring density, and very thin finished boards.

Typical production ranges are fab-dependent: microvias often 50–75 μm, line/space 25–50 μm at advanced shops. Limits are equally clear. Cycle count is highest. Yield is the lowest band. Registration and copper-fill quality are unforgiving. Basic FR-4 usually cannot stay. Cost is commonly a large step above 1+N+1 and can run several times a conventional board, depending on volume and spec. Published multipliers disagree across vendors; treat them as bands, not a single number.

Do not claim Any-layer is always more reliable. Stacked via count, fill quality, and z-axis CTE matter more here than in 1+N+1. Use it when density or thickness requires it, not as a status upgrade.

HDI Stackup Comparison Table

Compare these structures on decision criteria, not on a spec-sheet dump.

When each wins is simpler than the table. 1+N+1 wins when one escape layer per side is enough and schedule matters. 2+N+2 wins for most commercial fine-pitch programs because it adds channels without abandoning a core-based process. 3+N+3 wins after a trial route proves 2+N+2 is congested and you still want a core. Any-layer wins only when pitch, wiring density, or thickness cannot close at an acceptable layer count with i+N+i.

Industry cost multipliers for 1+N+1 often sit near a modest premium over conventional boards. 2+N+2 commonly lands higher. Any-layer quotes can run from about 2× to 6× conventional, depending on volume, fill density, material, and yield.

HDI Stackup Via Design: Stacked vs. Staggered Microvias

This comparison sits inside every 2+N+2 and Any-layer quote.

Staggered vias offset lands. They are usually preferred when space allows because stress is not concentrated in one copper column and the lower via does not have to be filled before the next laser hit. Stacked vias save vertical real estate under a BGA. They are required for many tight 2+N+2 fanouts and for Any-layer. They need filled, plated-shut vias and a controlled aspect ratio.

HDI Stackup Design for Manufacturability

Laser microvias are usually one dielectric layer deep. Skip vias are a different, harder process. If via diameter shrinks, build-up dielectric must shrink with it or aspect ratio walks out of the process window. Capture pads grow with sequential registration; alignment tolerance stacks with every extra cycle. Undersized pads are one of the most common CAM rejects.

Via-in-pad becomes necessary when BGA pitch leaves no dog-bone room. That decision pulls in copper fill and planarization. Dimples and solder wicking are assembly yield problems, not only fab cosmetics. Specify the dimple limit.

The N core is still useful. It carries power and ground, buried interconnect, and mechanical stiffness. Type II buries mechanical vias in the core so outer layers stay free. Residual PTH through the finished board remains useful for connectors, press-fit, thermal vias, and cheap interconnect. Those holes also steal routing and create stubs. Any-layer boards may minimize PTH. That is a cost and process choice, not automatically better.

HDI stackup materials follow the cycle count. 1+N+1 can often stay on mid-Tg or high-Tg FR-4. 2+N+2 and above usually need high-Tg, CAF-resistant, multiple-lamination-capable systems and low-profile copper for fine line. Any-layer and high-speed channels may need low-loss laminates. Do not default every Any-layer board to premium RF material if the nets do not require it.

Symmetry, copper balance, and thin dielectrics fight bow and twist after several press cycles. Finished thickness targets for mobile and industrial products pull in opposite directions from build-up count. Decide thickness before you add another "i."

HDI Stackup Cost: Layer Count vs. Build-Up Complexity

HDI price does not follow copper layer count. It follows how the board is built.

That is the relationship worth remembering. A stackup is a process plan. It tells the factory how many times the panel is pressed, laser-drilled, plated, and filled. Each extra build-up step adds work and risk. Extra copper layers add some work too, but they do not change the process family in the same way.

This is why two boards with the same layer count can sit in different price bands. An 8-layer 1+6+1 board and an 8-layer 2+4+2 board both have eight copper layers. The first has one HDI build-up on each side. The second has two. The second board needs another lamination cycle, another laser cycle, and often via fill. The factory is not selling "ight layers." It is selling a harder sequence.

The same logic applies as you move up the family:

• 1+N+1 is usually the lowest HDI premium. One microvia layer per side. Shortest extra process.
• 2+N+2 costs more because the second build-up is a second trip through laser, press, and registration. Stacked and filled vias raise that cost again. Staggered vias are typically the milder option.
• 3+N+3 is another step up the same ladder—more cycles, tighter alignment, thinner dielectrics.
• Any-layer HDI stackup is a different kind of board, not just "more layers." Almost every layer pair can take a microvia. Cycle count, fill quality, and yield all get harder, so price follows.

Layer count still matters, but as a secondary knob. Adding a conventional core layer is often cheaper than adding one more build-up. The core layer gives you routing, power, or a reference plane. The extra build-up gives you another HDI escape layer and another manufacturing cycle. If the design is short on planes, add layers. If the design cannot escape a fine-pitch BGA, add build-up. Mixing those two problems is how stackups get over-specified. Quotes also move with volume, material, factory capability, and yield. Those factors explain why two vendors price the same drawing differently.

How to Choose the Right HDI Stackup?

Use this order in a design review.

1.  Tightest component pitch and pin density, especially BGA/CSP

2.  Number of fine-pitch devices, not just the smallest one

3.  Required signal-layer count and reference-plane plan

4.  Board thickness and product envelope

5.  Speed, loss, and impedance class

6.  Reliability standard, such as consumer, auto, medical, Class 3

7.  Approved fab capability

8.  Cost and schedule

HDI Stackup Selection Decision Matrix

Choose 1+N+1 when density is moderate, BGAs are generally ≥0.4 mm, one HDI layer per side can finish escape, and yield dominates. Choose 2+N+2 when 0.3–0.4 mm-class parts appear, 1+N+1 escape fails, or high-speed interfaces need extra HDI layers. That is the best cost/capability balance for most commercial electronics. Choose 3+N+3 when multiple fine-pitch BGAs congest a proven 2+N+2 trial route and you still want a core-based process. Choose Any-layer HDI stackup when pitch, wiring density, or thickness cannot be met with sequential i+N+i at an acceptable layer count, and the program can pay for process, yield, and material.

HDI Stackup DFM: Common CAM Review Issues

Most HDI stackup issues are caught in CAM, before the board goes to press. The drawing may look finished in CAD, but the factory still has to confirm that the layer build, via plan, and impedance table can be made on a real panel.

The usual problems are easy to name. The file says HDI but does not state 1+N+1 or 2+N+2. Impedance was calculated on datasheet thickness, not the thickness after press. The stackup is heavier than the layout needs, or the vias do not match the stackup. Pads are too small for sequential lamination, copper is uneven, or via-in-pad is called out with no fill note.

The usual fix is also simple. Write the full stackup and via list. Adjust the dielectric stack, the impedance line width, or both so the target impedance can be hit after press. Drop an extra build-up step when fanout does not need it. Raise pad size and balance copper when warpage or registration is at risk.

AIVON runs that check before production. We calculate from the customer's stackup and impedance table, then send a short change proposal for approval. The goal is not to redesign the board. It is to lock a buildable HDI stackup before laser and lamination start.

Useful starting schemes, then customize:

Conclusion

An HDI stackup is a build plan. It sets how the board is pressed, drilled, and connected, but not how many copper layers it has.

Choose the simplest structure that can escape the parts, hold thickness, and meet impedance. 1+N+1 is the first step. 2+N+2 is the common production step. Any-layer is the last step, used only when the board cannot close any other way.

Confirm that plan in CAM before layout freeze. A stackup that can be built is cheaper to lock early than to change after the via grid is done.

FAQs

Q1: What is the difference between 1+N+1 and Any-layer HDI manufacturing process?

A1: 1+N+1 uses one sequential build-up cycle on each side of a conventional core that still contains mechanical through-holes. Any-layer HDI builds every layer sequentially with laser microvias, allowing interconnection between any layers and eliminating traditional through-holes for signal interconnects.

Q2: How many sequential build-up cycles are typically required for Any-layer HDI?

A2: Any-layer HDI requires a sequential build-up cycle for essentially every dielectric layer. An 8-layer Any-layer board may involve approximately 6–7 full build-up cycles after the initial core, with the number of cycles increasing as the layer count rises.

Q3: What are the most common failure modes in microvia plating during HDI production?

A3: Common microvia plating failures include incomplete fill, poor wall adhesion caused by residual smear, and plating-thickness variation that creates localized stress. These issues are controlled through thorough desmear, optimized copper-fill chemistry, stable process conditions, and effective post-plating planarization.

Q4: What process controls are essential to ensure reliable via filling in Any-layer boards?

A4: Critical controls include complete desmear, consistent electroless copper seed-layer coverage, optimized electrolytic copper-fill chemistry, precise current-density control, and post-plating planarization to minimize dimple depth. Cross-section inspection on each production lot helps verify via-fill quality and process stability.

Q5: How does the HDI manufacturing process impact overall board cost and lead time compared with conventional multilayer?

A5: Each sequential build-up cycle adds lamination, laser drilling, plating, and inspection steps, increasing both manufacturing time and cost. Moving from a conventional multilayer board to 1+N+1 HDI typically increases cost moderately, while Any-layer HDI can significantly increase cost and lead time because it requires more sequential cycles and tighter process controls.