High-speed 4-layer PCB routing works when the stackup gives every critical net a continuous reference and you treat the outer layers as microstrip. The usual arrangement—signal on layer 1, solid ground on layer 2, power on layer 3, signal on layer 4—puts top-layer traces a few mils above a solid ground. That keeps return current local and impedance predictable. Bottom-layer nets see the power plane instead. Power planes get split. Those splits become impedance discontinuities and larger return loops the moment a fast edge crosses them.
Four layers is the practical minimum for most multi-gigabit or DDR designs. Six layers give cleaner reference and less crosstalk, but cost and layer count constraints push a lot of boards to four. You can make it work. You just cannot ignore the reference plane under the traces.
Layer Assignment for High-Speed Nets
Put the fastest edges on the layer that references solid ground. On the standard stackup that is layer 1. Layer 4 nets reference the power plane. If that plane is solid under the entire run, the return still forms through interplane capacitance, but any split forces the current to detour. Keep clocks, high-speed serial pairs, and address/control buses on the ground-referenced side whenever possible.
When both outer layers must carry high-speed nets, stitch the power and ground planes with vias or capacitors near every layer transition. Orthogonal routing directions between layer 1 and layer 4 reduce broadside coupling. Horizontal on top, vertical on bottom is the usual practice. Long parallel runs on the same layer remain the bigger crosstalk source.
Figure 1 | Cross-section of a 4-layer stackup (Signal / Ground / Power / Signal)
Differential Pair Geometry and Length Matching
Differential impedance is set by trace width, intra-pair gap, and dielectric height to the reference plane. On typical 4-layer FR-4 with 4–5 mil core to the plane, 100 Ω differential pairs often land around 4–5 mil width and 5–8 mil gap. USB 90 Ω and PCIe 85 Ω shift the numbers. Calculate it for the actual stackup and fabricator tolerances; do not copy geometries from a different board thickness.
Keep the pair together. Same layer, same reference, same via style. Length match within the pair to the skew budget of the interface. On FR-4 microstrip the delay is roughly 150–170 ps per inch. A 10 ps budget therefore allows only a few mils of mismatch before you start adding serpentine. Serpentine itself should stay at least 3× trace width away from the pair so it does not create its own coupling. Inter-pair spacing of 5× the trace width (or more for multi-gigabit) keeps crosstalk between lanes acceptable.
Why the Return Path Must Stay Continuous
Above a few tens of megahertz the return current concentrates directly under the trace on the nearest plane. A continuous ground plane under a high-speed net keeps the loop area small and the impedance stable. Cross a split or void and the return detours. The sudden increase in loop area raises emissions and creates a local impedance bump that reflects energy.
The same thing happens at a layer change if no stitching via sits next to the signal via. The return has to find another path between planes. On a high-speed 4-layer PCB that path is often several millimeters away, enough to radiate and to degrade the eye. Place a ground via within a few millimeters of every high-speed signal via. For differential pairs, place the stitch vias symmetrically on both sides of the pair.
Figure 2 | Comparison of return current under a continuous reference plane versus the detour forced by a plane split or missing stitch via at a layer transition
Trace Length, Propagation Delay, and Timing
A trace becomes a transmission line once its length approaches a significant fraction of the edge rate. The usual rule of thumb is critical length ≈ rise time × velocity / 6. On FR-4 microstrip that velocity is about 6 inches per nanosecond, so a 1 ns edge starts looking like a transmission line beyond roughly an inch. DDR data-to-strobe matching, serial lane deskew, and clock-to-data timing all come down to controlling the actual electrical length, not just the physical length.
Layer changes matter here too. Microstrip on the outer layers is faster than a stripline would be because part of the field is in air. Mixing layers on a matched bus without accounting for the delay difference creates skew that no amount of length matching on one layer can fix. Keep matched groups on the same layer when the budget is tight.
Crosstalk from Spacing, Parallel Length, and Layer Choice
Outer-layer microstrip couples more strongly than stripline. Center-to-center spacing of 3× trace width is the common starting point for moderate-speed digital. Clocks and multi-gigabit serial usually need 5× or greater, or they should sit on opposite sides of the ground plane so the plane provides isolation. Parallel length multiplies the coupling. Short runs with tighter spacing often cause less trouble than long runs at the minimum spacing.
Orthogonal routing between the two signal layers cuts broadside coupling. Guard traces only help if they are stitched to ground at both ends and at intervals; an unstitched guard can increase coupling instead of reducing it.
Vias, Stubs, and Layer Transitions
Every via adds a discontinuity. On a 4-layer board the stub length is limited by the board thickness, but at multi-gigabit rates even a few tens of mils can resonate. Keep high-speed transitions to a minimum. When a via is required, place the stitch via next to it so the return follows the signal. For differential pairs, transition both members with identical via structures and symmetric ground vias.
Back-drilling removes the unused stub but is less common and more expensive on 4-layer boards. If the data rate is high enough that stubs matter, the better answer is usually fewer layer changes or a move to more layers with blind vias. Via-in-pad reduces pad-to-via stub length for BGA breakout, but confirm the fabricator can fill and plate it without adding excessive capacitance.
Figure 3 | Close-up of a high-speed signal via with adjacent ground stitching vias versus a via without return stitching, showing the local return current path
Routing Choices That Usually Fail First
90-degree corners are rarely the dominant problem on modern edge rates, but they still create a small impedance bump and an acid-trap risk in etching. 45-degree miters or arcs are cleaner and preferred. The larger failures are interrupted reference planes under the net, missing stitch vias at layer changes, and differential pairs that separate, change layers asymmetrically, or run over splits. Those create the reflections, skew, and emissions that show up in the eye diagram or on the pre-compliance scan.
On a high-speed 4-layer PCB the stackup and the reference continuity under every critical net set the limit. Geometry, length matching, and via treatment either preserve that limit or erode it. Check the return path under the fastest nets before you spend time optimizing serpentine or corner radius.
