PCB routing is often viewed as a matter of simply connecting the dots, and it can seem tedious and repetitive. That is only a basic view of the work. An experienced PCB design engineer must make many engineering decisions and resolve numerous signal-integrity, electromagnetic-compatibility, power-distribution, and manufacturability issues. The following guidelines summarize practical considerations for PCB routing, particularly for high-frequency, high-speed, and mixed-signal circuit boards.
1. General PCB Routing Practices
To achieve a reasonable layout and strong noise immunity in high-frequency, high-speed, and analog circuit boards, consider the following factors.
Layer Selection
Select the layer stackup appropriately. In high-frequency and high-speed PCB designs, using internal plane layers for power and ground can provide shielding, reduce parasitic inductance, and minimize crosstalk between signals.
Routing Geometry
Use 45-degree bends or curved bends where appropriate. This can reduce reflections and coupling in high-frequency and high-speed signals compared with abrupt routing changes.
Trace Length
Unless a special requirement applies, shorter traces are generally preferable. Where insertion loss or another signal-loss requirement exists, the trace length should be determined according to the actual design conditions. For adjacent traces, minimize the length over which they run in parallel whenever possible.
Via Design and Via Count
When designing vias, try to keep the via impedance consistent with, or as close as possible to, the impedance of the transmission line. The number of vias should also be minimized because vias can easily introduce impedance discontinuities.
Routing Direction Between Adjacent Layers
Routing directions on adjacent layers should preferably be perpendicular. For example, traces on one layer can run primarily horizontally while traces on the adjacent layer run vertically. This arrangement helps reduce coupling between signals on neighboring layers.
Ground Guarding
Ground guarding is often applied to important signal traces to improve immunity to interference. However, it can also introduce new problems. For example, a ground guard may reduce the available routing space or alter the local impedance. Before adding a guard trace, verify that it does not create an unwanted impedance change or otherwise interfere with the intended routing structure.
Interference sources can also be surrounded or isolated with grounded copper or guard traces so that they are less likely to disturb other signals.
Signal Loops
Signal routing should not form unnecessary loops. Reducing loop area limits the noise that can be coupled into the circuit and helps control electromagnetic radiation.
2. Routing Priority
Critical signals should be routed first. These typically include low-level analog signals, high-speed signals, clock signals, and synchronization signals.
A density-first approach is also useful. Begin with components that have the most complex connectivity, or start routing in the region with the highest connection density on the board.
- Whenever possible, provide dedicated routing layers for clocks, high-frequency signals, sensitive signals, and other critical nets. Keep their loop areas as small as possible. Manual priority routing, shielding, and increased spacing may be required to maintain signal quality.
- Avoid placing interference-sensitive signals in the electromagnetic environment between power and ground layers when that environment is unsuitable for the signal.
- Networks requiring impedance control should be routed according to their specified trace width and length requirements.
3. Clock Routing
Clock traces are among the most influential structures from an EMC perspective. Minimize the number of vias on a clock trace, avoid running it in parallel with other signal traces whenever possible, and keep it away from noise sources and heat sources that could interfere with signal quality. Clock traces should also be kept away from power circuitry to reduce mutual interference between the power network and the clock network.
If the board contains a dedicated clock generator, avoid routing traces directly beneath it. Copper can be placed beneath the device, and the ground structure may be isolated locally when necessary. Reference crystal oscillators used by many devices should also have no signal traces beneath them. A copper region can be used beneath the oscillator for isolation.
- Place the clock driver near the center of the PCB rather than at the board perimeter whenever practical. Keep the routing short and smooth, and avoid right-angle bends and T-shaped branches.
- Prevent interference between clocks and between clocks and other signals. Avoid parallel routing of these nets. Where necessary, use grounded shielding or guard traces for isolation, and maintain as much spacing as practical between different clocks and signals.
- Avoid routing clock signals across split reference planes.
- For differential clock traces, maintain matched length between the two members of the differential pair.
- For a clock crystal, route the clock signal through the load capacitor before it reaches the crystal. Provide surrounding vias and use a grounded shielding structure where appropriate.
- For clocks from the same source, place parallel-matching resistors close to the load device. Place series resistors close to the clock device or CPU.
4. Right-Angle Routing
Right-angle routing is generally avoided in PCB design and is often treated as an indicator of routing quality. The underlying reason is that a right-angle bend changes the effective trace width and therefore creates an impedance discontinuity.
Obtuse-angle and acute-angle routing can also produce impedance changes. The effect of a right-angle bend on signal transmission is mainly reflected in three areas:
- The corner can act as an equivalent capacitive load, increasing the effective delay and slowing the rise time.
- The impedance discontinuity can cause signal reflections.
- The sharp corner can contribute to electromagnetic interference.
5. Differential Routing
Differential signaling is increasingly common in high-speed circuit design, and many signal interfaces use differential-pair structures.
Differential routing improves immunity to interference for two main reasons.
First, for signals with the same voltage amplitude, the peak-to-peak differential voltage is twice the amplitude of a single-ended signal.
Second, a single-ended trace uses the ground plane as its reference. External interference therefore affects the signal and its return path differently, and the disturbances cannot necessarily cancel each other. A differential pair, by contrast, consists of two parallel traces with closely matched coupling. When both traces are exposed to the same interference source, the induced disturbances are similar. Because each trace is referenced to the other trace rather than directly to the ground plane, common-mode interference can be suppressed more effectively.
Differential routing can provide stronger noise immunity, lower bit-error rates, and higher transmission rates, but it requires an additional conductor compared with a single-ended signal path. The extra routing resources are therefore justified primarily when higher data rates or stronger noise immunity are required.
When designing differential transmission lines, PCB engineers must maintain matched length within each differential pair and keep the pair impedance consistent. Matched length helps the two differential signals maintain opposite polarity and reduces common-mode components. Consistent spacing helps maintain a stable differential impedance and reduce reflections.
Whether a tightly coupled or loosely coupled differential pair is preferable depends on the specific design conditions. The coupling structure should be selected according to the interface, stackup, impedance requirements, and surrounding routing environment.
6. Serpentine Routing
Serpentine traces are frequently used in PCB layout to adjust transmission-line delay. They are mainly used to achieve intra-pair or inter-net length matching and to meet system timing requirements.
7. Power and Ground Routing
A PCB may have an otherwise excellent signal layout, yet poor power and ground design can still introduce interference, degrade product performance, and even affect whether the design operates successfully. Power and ground routing should therefore be treated as core parts of the design rather than as secondary tasks.
Power and Ground Routing Rules
- Place decoupling capacitors between the power and ground networks.
- Use wide power and ground traces whenever possible. The ground trace should preferably be wider than the power trace.
- In high-speed digital PCBs, use wide ground conductors to form a low-impedance return path. A complete ground plane is preferable where possible. Analog ground should not automatically be treated in the same way; its connection must follow the system design.
- Use large copper areas for ground. Unused regions on the board can be connected to ground, or a multilayer board can dedicate separate layers to power and ground.
- In regions with dense via fields, prevent vias from connecting through clearance areas in the power and ground layers in a way that splits the plane. Plane fragmentation can reduce plane integrity and increase the return-path loop area of signal traces.
Ground-Return Loop Area
Keep the ground-return loop as small as possible. The loop formed by a signal trace and its return path should have minimal area. A smaller loop radiates less energy and is less susceptible to external noise.
Decoupling Capacitor Placement
- Add the necessary decoupling capacitors to filter interference on the power supply and stabilize the supply voltage. Decoupling-capacitor placement and power-routing topology directly affect overall system stability and can influence the success of the design.
- In general, the current path should pass through the filter or decoupling capacitor before reaching the powered device.
- In high-speed circuit design, the correct use of decoupling capacitors is closely related to the stability of the entire PCB.
8. Common Grounding for Digital and Analog Circuits
Many PCBs combine digital and analog circuitry rather than implementing only one type of function. Their mutual interference must therefore be considered during layout, especially noise coupling through the ground network.
Digital circuits generally contain higher-frequency activity, while analog circuits are often more sensitive to noise. High-frequency signal traces should therefore be kept as far as practical from sensitive analog components.
From the external-system perspective, the PCB may have only one ground connection to the outside world. The internal relationship between digital ground and analog ground must therefore be handled deliberately. In some designs, digital ground and analog ground are separated internally and connected at only one point near the external interface, such as a connector. In other systems, the grounds may not be connected on the PCB at all. The correct approach depends on the system architecture. If a single-point connection is used, the connection location and return-current paths must be considered carefully.
9. Routing Signals on Power or Ground Planes
In a multilayer PCB, most traces may already be completed on the dedicated signal layers. Adding another layer only for a small number of remaining traces can increase manufacturing effort and cost. One possible solution is to route signals on power or ground plane layers.
The power layer should generally be considered before the ground layer because preserving ground-plane integrity is usually more important. Avoid routing on the ground plane when doing so would fragment the plane or interrupt important return paths.
10. Design Rule Check
After routing is complete, carefully verify that the layout complies with the rules established by the designer. Also confirm that those rules are compatible with the PCB manufacturing process.
- Check whether the spacing between traces, traces and component pads, traces and through-holes, component pads and through-holes, and through-hole pairs is reasonable and meets manufacturing requirements.
- Verify that power and ground trace widths are appropriate. Check whether the power and ground planes are sufficiently coupled where required.
- Confirm that critical signals have received appropriate treatment, including trace length control, ground guarding, spacing between transmit and receive traces, and layer assignment where required.
- Check whether the analog and digital sections have independent ground structures or whether their connection method is appropriate for the system.
- Verify that manufacturing features have been added where required. Confirm that solder-mask openings and dimensions meet the process requirements, and ensure that silkscreen markings do not overlap component pads or affect assembly quality.
- Check whether the edges of power and ground planes on multilayer boards are properly recessed. Copper from an internal power or ground layer should not extend beyond the board edge, where it could create a short circuit.
11. Checking the 3W and 3H Guidelines
The 3W guideline states that the center-to-center spacing between signal traces should be three times the trace width.
The 3H guideline states that the center-to-center spacing between signal traces should be three times the distance from the trace to its reference plane.
Both the 3W and 3H guidelines are intended to reduce crosstalk between signal traces, particularly between high-speed or high-frequency nets. In compact products, however, it may be difficult to meet either guideline. In addition, crosstalk is not caused only by interaction between adjacent transmission lines; reference-plane discontinuities, return-path changes, vias, connectors, and other structures can also contribute.
PCB design involves trade-offs among signal integrity, power integrity, EMC, density, manufacturability, and cost. The appropriate routing method depends on the circuit function, stackup, interface requirements, and system architecture. These guidelines provide a practical starting point, but critical nets should still be evaluated against their specific electrical and manufacturing requirements.
