Impedance Design Software and Calculation Mode Selection

Controlled impedance and signal integrity field-solving design tools are used to predict PCB trace impedance before fabrication. The calculation model selected for a trace geometry affects how closely the modeled impedance matches the manufactured stack-up, particularly for outer-layer traces and offset stripline structures. This section introduces the impedance design software used for these calculations and the calculation modes most often applied in practical designs.

Highlights:

• Polar-Si8000 is the primary impedance design tool, with 93 calculation modes.
• Six modes are commonly used; outer-layer traces use the no-solder-mask-cover mode.
• Common configurations include edge-coupled surface microstrip and edge-coupled offset stripline.

Impedance Design Software

Controlled impedance and signal integrity field-solving design tools provide the basis for accurate transmission-line modeling. The primary impedance design software used in design work is Polar-Si8000. The software contains 93 impedance calculation modes in total. Of these, six modes are commonly used in design. For outer-layer traces, the no-solder-mask-cover mode is selected.

Selecting the correct mode ensures the calculated trace width and spacing correspond to the intended impedance target. The available modes cover many trace geometries, including microstrip and stripline variants.

Common calculation modes include:

Edge-Coupled Surface Microstrip 1B

Edge-Coupled Surface Microstrip 1B1A

Edge-Coupled Offset Stripline 1B2A

Impedance Design Pattern Selection

The first decision in any impedance calculation is not a number, it is a model. Before a trace width, a dielectric height or a copper thickness can mean anything, the calculator has to know which physical cross-section those numbers describe, because the same set of dimensions produces very different impedances depending on whether the trace sits on an outer layer over a single plane or is buried between two planes on an inner layer. Model selection therefore settles three things at once: which layers act as references, which dielectric layers contribute to the field, and which parameters the user is required to supply.

Two patterns cover a large share of practical differential-pair routing: the edge-coupled surface microstrip, designated 1B in the calculator's model library, and the edge-coupled offset stripline, designated 1B1A. The first describes a differential pair on an outer layer referenced to a single plane below it, with no solder mask over the copper. The second describes a differential pair on an inner layer referenced to planes both above and below it, with the pair deliberately offset rather than centered between them.

The two models are worth studying side by side because they show exactly how the parameter list grows with the complexity of the cross-section. The surface microstrip needs one dielectric height and one dielectric constant. The offset stripline needs two of each, plus a clear understanding of which height and which dielectric constant belong to which side of the trace. Everything else, the bottom and top trace widths, the edge-to-edge gap and the copper thickness, is entered in the same way in both models, so a designer who has learned one has effectively learned the trace definition used by the other.

Edge-Coupled Surface Microstrip 1B

The 1B pattern models a differential pair routed on the outermost copper layer, with the two traces side by side on the same layer, coupled along their facing edges, and referenced to a single ground or power plane underneath. The pair is described as a surface microstrip because one side of the trace faces air rather than dielectric, and as edge-coupled because the dominant coupling between the two lines of the pair is lateral, across the gap between them, rather than broadside between layers.

The "no solder mask" qualifier is part of the model definition rather than an optional setting. The calculation assumes the copper is bare, with no dielectric coating over the traces and no mask filling the gap between them. On a real board a mask is normally present, and its thickness and dielectric constant change the effective permittivity around the trace, which in turn shifts the impedance the pair presents. Selecting the bare-copper model while the fabricator applies a coating is one of the routine reasons a calculated value and a measured test coupon fail to agree, and the discrepancy is easy to misattribute to etching or laminate tolerances.

Parameter Definitions

• H1: the height from the impedance trace to its reference layer.
• Er1: the dielectric constant of the medium between the layers.
• W1: the bottom line width.
• W2: the top line width.
• S1: the line spacing, taken as the edge-to-edge gap between the two traces of the pair.
• T1: the copper thickness.

H1 is the dimension the field depends on most strongly in a microstrip cross-section, because it defines how far the return current path is from the trace and therefore how much of the field is stored in the dielectric rather than in the air above. In practice H1 is not a free variable chosen by the designer; it is whatever the stack-up produces after the layer assignment is fixed, which is why the dielectric height is normally read from the stack-up first and the trace geometry is then tuned to hit the target impedance.

Er1 plays the same role on the material side. It is the dielectric constant of the medium between the trace layer and the reference layer, and it is what converts the physical height H1 into an electrical distance. Because the microstrip has air above the trace, the effective permittivity seen by the field is a mixture of Er1 and the permittivity of air, which is why the same geometry on an inner layer and on an outer layer does not produce the same impedance.

Separate W1 and W2 entries exist because an etched trace is not rectangular. Copper is undercut during etching, so the trace is widest at the bottom where it meets the laminate and narrowest at the top. Supplying both widths lets the solver treat the conductor as a trapezoid and compute the field around the actual shape rather than an idealization of it. S1 and T1 complete the geometry: the gap sets the coupling between the two lines of the pair, and the copper thickness sets how much of the conductor sits inside the field region and how far the top surface of the trace is lifted away from the reference plane.

Worked Stack-Up Values

The entry below is a complete geometry for the 1B pattern. Each row is a single parameter, with the nominal value followed by the tolerance applied to it and the resulting minimum and maximum limits that the solver will use when it sweeps the design space.

Several features of this entry are worth pointing out. The bottom width is wider than the top width, which is the expected shape for an etched outer-layer trace. The gap S1 is larger than either width, so the pair sits in a loosely coupled regime where each line behaves close to a single-ended trace over the plane and the differential impedance is dominated by the individual line impedance rather than by the coupling. The copper thickness is entered as a single value, consistent with the model, which carries no separate parameter for a plating layer or a surface finish. The dielectric constant of 4.2 is applied to the full height H1.

Reading the Result and Tolerance Columns

Every tolerance field in this entry is set to zero, so the minimum and maximum columns simply repeat the nominal value. In that state the solver performs a single-point evaluation: the geometry is converted into one impedance figure, and there is no window to inspect. That is the correct setting when a stack-up is first being explored and the question being asked is simply "what does this geometry give me".

The moment non-zero tolerances are entered, the minimum and maximum columns stop mirroring the nominal and the calculation becomes a range calculation. Each parameter is then evaluated at the limits defined by its tolerance, and the Zdiff row returns a spread rather than a single number. That spread is the meaningful output for a production design, because a fabricated board will never hit the nominal dielectric height, the nominal etch width and the nominal copper thickness simultaneously. The width of the differential impedance window that the tolerance stack produces is the quantity that has to be compared against what the routing can accept, not the nominal figure on its own. Assigning realistic tolerances, taken from the laminate supplier's data and the fabricator's etch capability, is therefore part of the calculation rather than an optional refinement of it.

In this entry the Zdiff row reads 0.00 in both the minimum and maximum columns, which indicates that no impedance target has been associated with the configuration. The geometry has been captured, but the comparison against a target has not yet been made. Once a target is entered, the Calculate action attached to each row can be used to re-evaluate the impedance after any parameter is changed, without retyping the rest of the geometry.

Edge-Coupled Offset Stripline 1B1A

The 1B1A pattern models a differential pair routed on an inner layer, with reference planes on both of the adjacent layers. This is the adjacent-layer shielding configuration: the pair is enclosed above and below by copper, so the field is confined to the dielectric region around the traces instead of extending into the air above the board. The confinement has two consequences that matter at the layout level. Radiation from the pair and susceptibility of the pair to external fields are both reduced, and the impedance becomes insensitive to whatever is placed on the far side of the reference planes.

The pattern is called an offset stripline because the pair is not centered between the two reference planes. The dielectric height above the trace differs from the dielectric height below it, so the field distribution is asymmetric and the impedance cannot be described by a single height parameter. This is the normal situation in a real stack-up: the layer spacing above an inner-layer trace comes from one combination of core and prepreg, and the spacing below comes from another, and the two are rarely equal.

Parameter Definitions

• H1: dielectric height on one side of the trace.
• Er1: dielectric constant of the medium associated with H1.
• H2: dielectric height on the other side of the trace.
• Er2: dielectric constant of the medium associated with H2.
• W1: the bottom line width, defined exactly as in the 1B model.
• W2: the top line width, defined exactly as in the 1B model.
• S1: the line spacing, defined exactly as in the 1B model.
• T1: the copper thickness, defined exactly as in the 1B model.

W1, W2, S1 and T1 carry over unchanged from the surface microstrip model, so the trace definition does not have to be relearned when a pair moves from an outer layer to an inner layer. What changes is the dielectric description. The single H1 and Er1 pair of the microstrip becomes two pairs, and the critical step in filling in this model correctly is entering the right value for H1.

Worked Stack-Up Values

The entry below applies the same row structure to the offset stripline. Note that the dielectric data on the two sides of the trace are not the same: the two heights differ, and the two dielectric constants differ as well.

This entry returns a differential impedance of 99.60 ohms. Because all tolerances are zero, the minimum and maximum columns repeat that figure exactly, and the result is a single-point evaluation of the geometry as entered. The traces are narrower than in the surface microstrip example and the gap is again wider than the trace width, so the pair remains in a loosely coupled regime in which the impedance of each line against its reference planes still dominates the differential result. The copper thickness is substantially lower than in the outer-layer example, which is consistent with an inner-layer trace that has not been through via plating and surface finishing.

Why H1 and H2 Must Be Entered Correctly

H1 and H2 share one property: both are dielectric thicknesses. That is where the similarity ends. They describe the dielectric on opposite sides of the trace, and in the offset stripline the two sides are built from different materials in different combinations. When the thicknesses of the core and the prepreg are not equal, which is the usual case, entering H1 and H2 correctly and in the right order becomes critical. The two heights are not interchangeable.

The reason is structural. The offset stripline model assumes a specific correspondence between each height, its dielectric constant, and the position of the trace relative to the two reference planes. If the values are swapped, the solver is effectively handed a mirrored stack-up, in which the trace sits closer to the plane it is actually further from and is surrounded by the wrong dielectric on each side. The calculation still returns a number, and that number looks perfectly plausible, but it belongs to a cross-section that does not exist on the board. There is no error message to flag the mistake, because from the solver's point of view nothing is wrong.

The same reasoning applies to Er1 and Er2. In the worked entry above the two dielectric constants are 4.2 and 3.85, values that differ because the core and the prepreg are different materials. Pairing a height with the wrong dielectric constant produces the same silent class of error as swapping the heights themselves. The safe procedure is to read the stack-up from the fabrication drawing, identify which dielectric layer lies immediately above the trace layer and which lies immediately below it, and enter each height together with the dielectric constant of that same layer.

A further point follows from the asymmetry itself. Because the field around the trace is not distributed symmetrically, the offset stripline is more sensitive to one height than to the other, and the sensitivity depends on which side the trace is closer to. A small change in the thinner dielectric moves the impedance appreciably, while the same absolute change on the thicker side moves it much less. This is why the tolerance columns deserve more attention in the 1B1A model than in the 1B model: the two heights do not contribute equally to the impedance window, and the tolerance that dominates should be the one that receives the tighter impedance process control.

The choice between the two patterns ultimately follows from the routing decision itself. A pair that must run on an outer layer, whether for fan-out reasons or because it has to reach a connector on the surface, uses the 1B model and one dielectric height, accepting that the mask and the open air above the trace are part of the impedance. A pair that can be routed on an inner layer uses the 1B1A model, gains the shielding of the two adjacent reference planes, and pays for it with a second dielectric height and a second dielectric constant that must both be read correctly from the stack-up. Getting the model right and then filling in the parameters in the right order is the part of impedance design that no amount of later tuning can repair.

Impedance Design Mode Selection (Appendix)

The process begins with the core.

Film lamination follows.

The etchant flow direction is indicated.

Film stripping follows.

Exposure, development, and etching are shown next.

During production, the etchant contacts the copper surface sufficiently, while contact with the underside is relatively weak. As a result, the etched line width is trapezoidal, and W1 > W2. This trapezoidal cross-section changes the conductor width from top to bottom. The lower line width W1 contacts the core. Therefore, H1 in the impedance calculation software is the core thickness, and Er1 and Er2 are the dielectric constants of the corresponding media.

Related Reading: 

Definition and Design Purpose of Characteristic Impedance in PCBs