Controlled impedance is one of the few PCB characteristics that must be agreed upon by the designer and the fabricator before the first drill hit. The stackup defines a target value, but the value that actually reaches the tester is the product of a chain of fabrication variables, each of which shifts the geometry and the material properties that determine characteristic impedance. A board can be designed correctly and still miss its tolerance window because the etched line came out narrow, the prepreg pressed thinner than nominal, or the solder mask was printed twice instead of once.
This article works through the manufacturing parameters that influence impedance — line width, line spacing, copper thickness, dielectric thickness, dielectric constant, and solder mask — and explains the direction and relative weight of each contribution. It then covers the practical control methods used in fabrication: etch compensation, plating balance, prepreg selection, and lamination control. The goal is to give designers and process engineers a shared vocabulary for the trade-offs, so that the impedance target, the stackup, and the fabrication tolerances are set with realistic expectations rather than hopeful ones.
Highlights:
- Dielectric thickness is the single most influential manufacturing variable for impedance, followed by line width and copper thickness; line width must be held within a ±10% tolerance to make impedance control achievable.
- Impedance moves in opposite directions with geometry and material: wider lines and thicker copper lower Z0, while thicker dielectric and lower dielectric constant raise it.
- Solder mask is a real but bounded contributor — one print lowers single-ended impedance by roughly 2 ohms and differential impedance by 8 ohms, and beyond three prints the value stops changing.
From the Fabrication Perspective: The Key Factors
Every impedance model, whether a field solver or a fabricator's empirical curve, is built from the same four cross-section dimensions. In fabrication terms, the parameters that determine the impedance of a trace are:
- Line width (w)
- Line spacing (s)
- Line thickness, or copper thickness (t)
- Dielectric thickness (h)
The fifth parameter is the dielectric constant. Relative permittivity, εr, is commonly referred to in the industry as Dk. It describes how the insulating material responds to the electric field around the trace, and it is a material property rather than a geometric one.
Solder mask also affects impedance, although it is usually folded into the dielectric constant discussion. The mask is applied directly on top of the dielectric, and its presence raises the effective permittivity seen by the trace. Treated this way, the effect is a reduction of the impedance value — typically the impedance value decreases by 4% accordingly. Assigning the effect to Dk rather than treating it as a separate parameter keeps the design model simple without ignoring a real contribution.
The Direction of Each Relationship
The cross-section above supports four direct relationships, and knowing the direction of each is the basis for any process adjustment:
- Z0 is inversely proportional to line width w: the wider the line, the lower Z0.
- Z0 is inversely proportional to copper thickness: the thicker the copper, the lower Z0.
- Z0 is directly proportional to dielectric thickness h: the thicker the dielectric, the higher Z0.
- Z0 is inversely proportional to the square root of the dielectric constant: the higher the Dk, the lower Z0.
Impedance Versus Each Influencing Factor
1. Dielectric Thickness — The Dominant Factor
Dielectric thickness is the most influential factor in impedance. Increasing the dielectric thickness raises impedance, and reducing it lowers impedance. This dominance is partly a matter of physics and partly a matter of how much variation the process allows: the distance between the trace and the reference plane varies more, in percentage terms, than the etched width typically does.
Different prepregs carry different resin contents and different thicknesses. The thickness achieved after lamination depends on the flatness of the press and on the lamination program, so the nominal figure on a datasheet is only a starting point. For any laminate that will be used, the achievable dielectric layer thickness must be established first so that the design calculation is based on what the process can actually deliver. Three things govern dielectric thickness in production: the engineering design, the lamination control settings, and incoming material tolerance.
2. Line Width
Increasing line width reduces impedance; reducing line width increases impedance. Line width must be controlled within a ±10% tolerance for the impedance target to be met reliably. This tolerance is the practical boundary between a controllable process and one that merely hopes to land inside the specification window.
Line width is primarily controlled through etching. To hold the width, the working film is given process compensation that accounts for the etch undercut, the photoplotting error, and the image transfer error, so that the final etched width lands on the target rather than the artwork dimension.
Local defects matter as much as the average. A notch in a signal line affects the entire test waveform: the single-point impedance at the notch reads high, which makes the whole waveform uneven. Impedance lines must not be repaired or touched up, and the notch must not exceed 10%.
3. Copper Thickness (Line Thickness)
Reducing copper thickness increases impedance, and increasing it reduces impedance. Copper thickness is set either by pattern plating or by selecting a base foil of the appropriate thickness. What matters most is uniformity: the thickness must be even across the panel, because a local variation changes the local impedance and shows up as ripple on the time-domain profile.
For boards carrying fine lines and isolated traces, current-sharing blocks are added to balance the current during plating and prevent uneven copper thickness along the traces. When copper distribution on the CS and SS sides is extremely uneven, the panels are cross-loaded — rotated between passes — so that both sides end up with a comparable copper thickness.
Dielectric Constant
Increasing the dielectric constant reduces impedance, and reducing the dielectric constant raises impedance. Dk is controlled through material selection rather than through process adjustment, which makes it a design decision as much as a fabrication one.
Different laminates have different dielectric constants depending on the resin system used. FR-4 sits in the range of 3.9 to 4.5, and its Dk falls as the operating frequency rises. PTFE-based laminates range from 2.2 to 3.9. When a signal requires high transmission performance and a correspondingly high impedance value, a low dielectric constant is required — which is why high-speed designs move away from standard FR-4 toward lower-Dk materials.
Solder Mask Thickness
Printing solder mask reduces the impedance of the outer layers. Under normal conditions, one print of solder mask lowers single-ended impedance by 2 ohms and differential impedance by 8 ohms. Printing twice doubles those reductions. Once the mask has been printed three times or more, the impedance value no longer changes. The effect is real but self-limiting, which is why it can be handled as a fixed offset in the design model.
The Relative Weight of Each Parameter
The parameters above do not contribute equally. Dielectric thickness carries the greatest leverage, followed by line width and copper thickness, with the dielectric constant fixed by material choice and the solder mask contributing a bounded offset. The chart below summarizes how the parameters compare in terms of influence, which is what determines where process control effort should be concentrated.
Other Factors to Consider in Impedance Design
Impedance control does not exist in isolation. Several design and manufacturing constraints interact with it, and an impedance target that ignores them is likely to be unbuildable or unusable:
- Whether the line width can satisfy the current-carrying requirement.
- Whether the stackup structure is reasonable.
- Mutual interference between signal layers.
- The routing density the board requires.
- The choice of laminate and prepreg type.
- Whether the interlayer dielectric thickness can be achieved in production.
- Whether the final board thickness meets the customer's requirement.
These items overlap with the impedance discussion because they compete for the same degrees of freedom. A wider line helps with current and impedance but complicates routing density. A thicker dielectric helps impedance but affects the total board thickness and the achievable layer count. Settling the impedance target without settling these constraints in parallel usually produces a stackup that has to be renegotiated during fabrication.
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