Every buck converter requires input capacitance. In a purely theoretical scenario where the upstream supply has zero output impedance and infinite current capability, and the PCB interconnect has zero resistance and inductance, an input capacitor would not be necessary. In practice, such conditions never occur, so you should assume that a buck converter needs an input capacitor.
The input capacitor stores charge that supplies current pulses when the high-side switch is on. When the high-side switch turns off, the input source recharges the input capacitor (Figure 1).
Figure 1 | Simplified input-capacitor current waveform during a buck converter switching cycle, assuming the output inductance is infinite. Source: Texas Instruments
The switching action charges and discharges the input capacitor, causing its terminal voltage to rise and fall. This voltage variation appears as input voltage ripple at the converter's switching frequency. The input capacitor filters the pulsed input current to minimize ripple on the upstream supply voltage.
The capacitance value largely determines the ripple amplitude, and the capacitor's ratings must tolerate the associated RMS current. A common introductory RMS current estimate assumes a single input capacitor with no equivalent series resistance (ESR) or equivalent series inductance (ESL). In reality, finite output inductance produces input-side ripple current as well, as illustrated in Figure 2.
Figure 2 | Power Stage Designer shows input capacitor ripple current and the computed RMS current. Source: Texas Instruments
Current Sharing Among Parallel Input Capacitors
Most real designs use multiple input capacitors in parallel to achieve the required effective capacitance. A typical combination includes a small high-frequency multilayer ceramic capacitor (MLCC), for example 100 nF, one or more larger MLCCs such as 10 μF or 22 μF, and sometimes a polarized bulk capacitor such as 100 μF.
Each capacitor serves a related but distinct function. The high-frequency MLCC decouples fast transient currents caused by MOSFET switching in the DC/DC converter. The larger MLCCs deliver current pulses at the switching frequency and its harmonics. When the input source impedance is too high to respond quickly to load transients, the bulk capacitor supplies the transient current demanded by the output load.
Bulk capacitors typically have significant ESR, which introduces damping and reduces the Q factor of the input filter. Depending on the relative impedance at the switching frequency compared with the MLCC branch, the bulk capacitor can also carry substantial RMS current at the switching frequency.
Bulk capacitor data sheets specify maximum RMS current ratings to limit self-heating and ensure lifetime is not reduced. MLCCs have much lower ESR, so their self-heating due to RMS current is typically smaller. However, designers sometimes overlook the maximum RMS current limits that ceramic capacitor data sheets specify. It is therefore important to understand the RMS current in each individual input-capacitor branch.
When you use multiple larger MLCCs, you can combine them and enter the equivalent capacitance into a current-sharing calculator to estimate RMS currents in the parallel input capacitor branches. These RMS calculations often consider the fundamental switching frequency only. Even so, such a tool is a useful step beyond single-capacitor RMS estimates.
Consider an example with VIN = 9 V, VOUT = 3 V, IOUT = 12.4 A, fSW = 440 kHz, and L = 1 μH. The three parallel input capacitors are: 100 nF (MLCC) with ESR = 30 mΩ and ESL = 0.5 nH; 10 μF (MLCC) with ESR = 2 mΩ and ESL = 2 nH; and 100 μF (bulk) with ESR = 25 mΩ and ESL = 5 nH. ESL values include PCB trace inductance.
Figure 3 shows the current-sharing calculator results for this case. As expected, the 100 nF capacitor carries a very small RMS current of about 40 mA. The larger MLCC and the bulk capacitor share the RMS current more evenly, at 4.77 A and 5.42 A respectively.
Figure 3 | Output of the Power Stage Designer capacitor current-sharing calculator. Source: Texas Instruments
In practice, MLCC capacitance decreases under applied DC voltage (DC bias). For example, a 10 μF, 25 V X7R MLCC in an 0805 package may deliver only 30% of its rated capacitance at a 12 V bias. In that case, the bulk capacitor's branch current can rise to 6.38 A, potentially exceeding its RMS rating.
A practical remedy is to use a larger case size and multiple capacitors in parallel. For example, a 10 μF, 25 V X7R MLCC in a 1210 case may retain about 80% of its rated capacitance at 12 V bias. Using three such devices as the C2 branch yields an effective 24 μF in the calculator.
Paralleling these capacitors reduces the bulk capacitor's RMS current to about 3.07 A, which is easier to manage. Placing three 10 μF MLCCs in parallel also reduces the C2 branch ESR and ESL by approximately a factor of three.
The 100 nF MLCC's small capacitance and relatively higher ESR mean it contributes little current at the switching frequency and its lower-order harmonics. Its primary role is to decouple nanosecond-scale current transients that occur at MOSFET switching edges, which is why designers often call it the high-frequency capacitor.
For this high-frequency function, place the smallest-case, lowest-ESL capacitor as close as possible to the regulator's input voltage and ground pins, and minimize the PCB loop inductance with very short traces or a tight via-in pad connection to power and ground planes. Otherwise, parasitic inductance in the interconnect will prevent this capacitor from effectively decoupling the high-frequency spectrum of the switching edges.
Smaller-value capacitors also have higher self-resonant frequencies, which helps target higher-frequency decoupling based on their ESR and impedance curves. Likewise, place the larger MLCCs as close to the converter as possible to minimize parasitic inductance and improve their effectiveness at the switching frequency and its harmonics.
Figure 3 also highlights an important point: if you treat the total input capacitance as one equivalent capacitor, the overall RMS input current may be 6 A, but the sum of the RMS currents in branches C1, C2, and C3 can exceed 6 A. This is not a violation of Kirchhoff's current law (KCL); KCL applies to instantaneous currents. RMS currents are time-averaged magnitudes and, for time-varying and phase-shifted branch currents, their RMS values do not add arithmetically to the RMS of the sum.
Simulation With TINA-TI and PSpice for TI
If your application requires more than three input capacitor branches, circuit simulation is a practical way to compute RMS currents. Tools such as TINA-TI and PSpice for TI can calculate RMS currents that include the fundamental switching frequency and harmonics, and they support more detailed capacitor models that capture frequency-dependent ESR and ESL.
In TINA-TI, you can compute RMS current in each capacitor branch by running a transient simulation, selecting the desired branch current waveform in the output window, and then choosing the average/RMS calculation from the Process menu. TINA-TI evaluates the RMS over the visible time interval using numerical integration between the start and end display times.
Figure 4 shows a representative simulation view. For clarity, the 100 nF capacitor is omitted because its current is very small and can introduce ringing around switching edges that obscures the main waveforms. The Power Stage Designer analysis of the total input-capacitor branch current yields an input current IIN of 6 A RMS, consistent with Figure 2.
Figure 4 | TINA-TI output showing capacitor branch current waveforms and the computed RMS current in C2. Source: Texas Instruments
Compared with an idealized trapezoidal current waveform that ignores ESR and ESL, the actual capacitor branch currents differ significantly. This behavior matters for DC/DC converters such as TI's LM60440, which provide two parallel input voltage (VIN) and ground (GND) pins.
Layout Considerations for Dual-Input-Pin Converters
A mirrored pinout allows two identical parallel input loops. You can place paired input capacitors (both the high-frequency and bulk/MLCC network) adjacent to each PVIN–PGND pair. Two parallel current loops halve the effective parasitic inductance of the input path.
In addition, the two mirrored input loops create equal and opposite magnetic fields, which partially cancel the H-field, further reducing parasitic inductance (Figure 5). However, as Figure 4 indicates, if you do not carefully match the capacitance, ESR, ESL, and layout of the parallel branches to achieve equal parasitic impedance, branch currents can differ widely.
Figure 5 | Symmetric "butterfly" layout with parallel input and output loops. Source: Texas Instruments
Notes on Software Tool Usage
To correctly specify a buck converter's input capacitors, you must know their RMS currents. You can estimate these currents analytically or, more simply, by using software such as Power Stage Designer. This tool can also estimate currents in up to three parallel input-capacitor branches, which reflect common real-world designs.
For more complex cases, TINA-TI or PSpice for TI can include harmonics, frequency-dependent parasitics, and additional parallel branches. These simulations also illustrate why, in mirrored "butterfly" input layouts, it is important to match the input capacitor combinations and routing so that the parallel loops have similar parasitic impedance and share current as intended.
In summary, selecting and placing input capacitors is not only about meeting a target capacitance. It requires understanding branch RMS currents, the impact of ESR and ESL, DC bias effects on MLCCs, and how layout influences parasitic inductance and current sharing. Using both calculator-style tools and circuit simulation helps ensure that each capacitor operates within its ratings while the converter meets input ripple and transient performance goals.
