Printed circuit boards remain the primary assembly platform for the electronics used across today's equipment and systems. Experience shows that a correct schematic is not sufficient on its own: if the board is laid out poorly, the reliability of the finished product will suffer. Two thin traces routed close together in parallel, for example, introduce a delay in the signal waveform and produce reflected noise at the far end of the transmission line. In that sense the layout behaves as part of the circuit, and it must be designed with the same discipline as the schematic.
This article covers the internal EMC design techniques that apply at board level: grounding strategy for mixed-signal boards, electromagnetic compatibility measures expressed through trace geometry and routing, decoupling capacitor configuration, board dimensions and component placement, and thermal design of the assembled board.
Highlights:
- Grounding topology must follow the signal's operating frequency: single-point grounding below 1MHz, distributed multi-point grounding above 10MHz, and a wavelength-limited ground lead in between.
- Transient current interference is dominated by the inductance of the trace, so short and wide routing, together with a grid-style layer structure, suppresses both impulse noise and crosstalk.
- One decoupling capacitor per IC, a bulk electrolytic capacitor at the supply entry, and short capacitor leads form the baseline reliability practice for a digital board.
Internal EMC Design: Why Layout Decides Reliability
Electromagnetic compatibility (EMC) is the ability of electronic equipment to operate cooperatively and effectively in a variety of electromagnetic environments. EMC design has two complementary goals. The first is to suppress interference arriving from outside the equipment so that the product continues to work normally in its specified electromagnetic environment. The second is to reduce the electromagnetic interference that the equipment itself emits toward other equipment. Both goals are decided largely at the board level, long before the enclosure and cabling are finalized.
Ground Design
Grounding is the most important method of controlling interference in electronic equipment. When grounding and shielding are combined correctly, most interference problems can be solved. The ground structures found in electronic equipment fall roughly into system ground, chassis ground (shield ground), digital ground (logic ground) and analog ground. Four points deserve attention during ground design.
Choosing Between Single-Point and Multi-Point Grounding
In low-frequency circuits, where the signal operating frequency is less than 1MHz, the inductance of the wiring and of the connections between devices has little influence, while the circulating currents formed by the ground circuit influence interference strongly. Single-point grounding should be used in this case. When the signal operating frequency is greater than 10MHz, the ground trace impedance becomes very large; the objective then shifts to minimizing that impedance, which calls for distributed multi-point grounding to the nearest ground. In the 1MHz to 10MHz band, single-point grounding remains acceptable only if the ground lead length does not exceed 1/20 of the wavelength; otherwise the multi-point method must be adopted.
Separating Digital and Analog Circuits
A board often carries both high-speed logic circuits and linear circuits. They should be placed as far apart as possible, and their ground returns must not be mixed; each should be connected separately to the ground at the power supply end. The grounding area devoted to the linear circuit should be made as large as practical, since a generous ground plane lowers the impedance seen by sensitive analog nodes.
Widening the Ground Trace
If the ground trace is thin, the ground potential shifts with changes in current, which makes the timing signal level of the equipment unstable and degrades its noise immunity. The ground trace should therefore be made as wide as possible, so that it can carry three times the current permitted on the printed circuit board. Where the layout allows, the ground trace width should be greater than 3mm.
Closing the Ground Trace into a Loop
When designing the ground system of a board that contains only digital circuits, forming the ground trace into a closed loop noticeably improves noise immunity. The reason is that a digital board carries many integrated circuits, and components that draw heavy current are limited by the width of the ground trace. A large potential difference then develops across the ground structure, and noise immunity drops. Closing the ground structure into a loop reduces that potential difference and restores the noise immunity of the equipment.
Electromagnetic Compatibility Design
Selecting a Reasonable Trace Width
The impulse interference that transient currents produce on a printed trace is caused mainly by the inductive component of that trace, so the inductance should be reduced as far as possible. The inductance of a trace is proportional to its length and inversely proportional to its width; short and wide traces are therefore the favorable geometry for interference suppression. Clock lines, row driver lines and bus driver signal lines frequently carry large transient currents, and their traces must be made as short as the layout permits.
For circuits built from discrete components, a printed trace width of around 1.5mm fully satisfies the requirement. For integrated circuits, a trace width between 0.2mm and 1.0mm can be selected, depending on the current carried and the available routing space.
Using the Correct Routing Strategy
Parallel routing reduces the inductance of the individual trace, but it increases the mutual inductance and distributed capacitance between adjacent traces. Where the layout allows, a grid-style mesh routing structure is preferred: route horizontally on one side of the board and vertically on the other, then connect the crossing points with metallized holes. To suppress crosstalk between traces on the printed circuit board, long-distance parallel runs should be avoided during routing.
Decoupling Capacitor Configuration
In a DC supply loop, changes in the load induce noise on the supply. In a digital circuit, when the circuit switches from one state to another, a large spike current is drawn on the supply line, which forms a transient noise voltage. Configuring decoupling capacitors suppresses the noise generated by load changes; it is a standard practice in the reliability design of printed circuit boards. The configuration principles are as follows.
- Connect an electrolytic capacitor of 10uF to 100uF across the supply input. If the board position allows, an electrolytic capacitor of 100uF or more gives better interference suppression.
- Provide each integrated circuit chip with a 0.01uF ceramic capacitor. If the board is too small in area to fit them, one 1uF to 10uF tantalum electrolytic capacitor may be configured for every 4 to 10 chips. Such devices have a particularly low high-frequency impedance, presenting an impedance of less than 1Ω over the 500kHz to 20MHz range, and their leakage current is very small, below 0.5uA.
- For devices with weak noise immunity and large current changes at turn-off, and for memory-type devices such as ROM and RAM, a decoupling capacitor should be connected directly between the Vcc and GND pins of the chip.
- The leads of a decoupling capacitor must not be too long. High-frequency bypass capacitors in particular must not be fitted with leads.
Board Size and Component Placement
The size of the printed circuit board must be moderate. If it is too large, the printed traces become long and the impedance rises, which not only degrades noise immunity but also raises cost. If it is too small, heat dissipation is poor and the board becomes more susceptible to interference from nearby traces.
Component placement follows the same logic as in other logic circuits: devices that are related to one another should be placed as close together as possible, which yields better noise immunity. The clock generator, the crystal oscillator and the clock input of the CPU are all prone to generating noise and must be placed close to one another. Noise-generating devices, low-current circuits and high-current circuits should be kept as far as possible from the logic circuits; where possible they should be built on a separate board. This last point is particularly important.
Thermal Design
From the standpoint of heat dissipation, the printed circuit board is best mounted vertically, and the distance between adjacent boards should generally not be less than 2cm. The arrangement of devices on the board should follow a defined set of rules.
- For equipment cooled by free convection, integrated circuits and other devices are best arranged lengthwise; for equipment using forced air cooling, they are best arranged crosswise.
- Devices on the same board should be grouped according to their heat output and their tolerance to heat. Devices that generate little heat, or that tolerate heat poorly (small-signal transistors, small-scale integrated circuits, electrolytic capacitors), belong at the upstream end of the cooling airflow, at the inlet. Devices that generate a great deal of heat, or that tolerate it well (power transistors, large-scale integrated circuits), belong furthest downstream.
- In the horizontal direction, high-power devices should be placed as close as possible to the edge of the board so that the heat conduction path is shortened. In the vertical direction, high-power devices should be placed as close as possible to the top of the board so that their influence on the temperature of other devices during operation is reduced.
- Devices that are sensitive to temperature are best located in the coolest region, for example at the bottom of the equipment. They must never be placed directly above a heat-generating device, and multiple devices are best staggered in the horizontal plane.
- Heat dissipation from the boards inside the equipment relies mainly on air movement, so the airflow path must be studied during design and devices or boards configured accordingly. Air always tends to flow where resistance is lowest, which means that when devices are configured on the board, large empty regions in any one area should be avoided.
Taken together, these five areas of board-level design act on the same objective. A ground structure matched to the signal frequency, trace geometry chosen for low inductance, decoupling placed at the source of the transient, a moderate board size with related devices grouped closely, and an airflow path that respects the thermal hierarchy all reduce the coupling paths that turn a correct schematic into an unreliable product.
Related Reading:
EMC Engineer Skills and Common Components: Chokes, Ferrite Beads, Filter Capacitors
EMC Design Principles and EMI/EMC Questions for PCB Engineers
PCB EMC Design Q&A: Differential Pairs, Grounding and Filtering
FCC and EMC Compliance Requirements Explained for PCB Design
Ferrite Beads vs. Inductors for High-Frequency Filtering on PCBs
Class-D Amplifier PCB Routing: EMC, Power, and ESD Essentials
EMC Fundamentals: Disturbance and Interference Control Terms
EMC Measurement, Equipment Classification, and Transceiver Terms
Power Control, Supply Impedance, and Flicker Terminology Explained
