This article answers practical questions that arise when designing PCBs for electromagnetic compatibility. It covers differential signal routing, grounding strategy, high-speed high-density routing, power filtering, and stackup choices that reduce emissions. The discussion is intended for designers who must balance signal integrity, EMC performance, and manufacturing cost. Readers will learn why certain layout practices are recommended, when a rule can be relaxed, and how decisions made during the early layout stage affect later compliance.
Highlights:
- Differential pairs depend on field coupling. A ground trace placed between the two lines disrupts flux cancellation and noise immunity.
- Chassis ground connections should shorten the return current path. Mounting screws near clocks and high-frequency devices are often used for this purpose.
- EMC cost is driven by stackup, filtering components, and mechanical shielding. Slow slew rates, impedance control, and proper return paths reduce radiated emissions.
Can a Ground Trace Be Added Between Differential Signal Lines?
In general, a ground trace should not be placed between the two lines of a differential pair. Differential signaling relies on coupling between the two conductors. The two lines are routed close together so that their electromagnetic fields interact. This coupling provides flux cancellation, which reduces the effective loop area, and it provides noise immunity because common-mode disturbances tend to affect both lines similarly. If a ground trace is inserted between the pair, the coupling effect is broken. The field distribution changes, and the pair no longer receives the full benefit of flux cancellation and noise rejection. For this reason, the space between differential lines should normally be kept free of ground traces.
What Principles Should Guide the Selection of PCB-to-Chassis Ground Points?
The selection of PCB-to-chassis ground points should follow one main principle: use chassis ground to provide a low-impedance path for return current and to control the path that this return current takes. Return current tends to flow along the path of least impedance, which is usually the reference plane directly beneath the signal trace. If the return path is forced to detour, the current loop area increases, and the structure radiates more effectively. A common practice is to connect the PCB ground plane to chassis ground with mounting screws near high-frequency devices or clock generators. This shortens the return path for high-frequency currents and reduces the overall current loop area. The result is lower electromagnetic radiation.
What Techniques Apply to High-Speed (>100 MHz) High-Density PCB Design When Board Size Is Fixed?
When a fixed board size must accommodate more functions, routing density usually increases. Higher density can strengthen interference between traces, and narrower traces make it difficult to reduce impedance. In high-speed high-density PCB design, crosstalk requires particular attention because it affects timing and signal integrity. Several practices help control the problem.
First, control the continuity and matching of trace characteristic impedance. Any discontinuity along a high-speed trace causes reflection and can increase radiation. Second, choose trace spacing carefully. A spacing of twice the trace width is commonly used as a starting point. Simulation can show how spacing affects timing and signal integrity, and it can help identify the minimum tolerable spacing. Results may differ for different chips and different signals. Third, select an appropriate termination scheme. Termination reduces reflections and helps preserve signal quality. Fourth, avoid routing adjacent layers in the same direction, and especially avoid traces that overlap directly above and below each other. Crosstalk between overlapping traces on adjacent layers can be larger than crosstalk between adjacent traces on the same layer. Fifth, use blind and buried vias to increase routing area. This can free space for more interconnections, but it increases PCB fabrication cost.
In practice, perfectly parallel and equal-length routing is difficult to achieve. Even so, the layout should approach these conditions as closely as possible. In addition, reserve differential termination and common-mode termination to mitigate the effects on timing and signal integrity.
Why Does an LC Filter Sometimes Perform Worse Than an RC Filter at Analog Power Supplies?
Comparing LC and RC filters requires considering the frequency band to be filtered and whether the inductance value is appropriate. The reactance of an inductor depends on both its inductance and the frequency. At higher frequencies, the reactance is larger and the inductor blocks noise more effectively. If the power noise is at a low frequency and the inductance is not large enough, the LC filter may perform worse than an RC filter. The RC filter uses resistance to dissipate noise energy and can be effective at lower frequencies. However, RC filtering has costs. The resistor dissipates energy, so efficiency is lower, and the selected resistor must be able to handle the power it dissipates. The designer must check the resistor power rating as part of the selection.
How Should Inductor and Capacitor Values Be Selected for PCB Filtering?
Inductance selection must consider not only the noise frequency to be filtered but also the ability to respond to transient current. An inductor resists changes in current. If the LC output may need to deliver a large current suddenly, too large an inductance will slow the current through the inductor and increase ripple noise. The inductance value therefore has to be chosen with both filtering and transient response in mind. Capacitance depends on the allowable ripple noise specification. A tighter ripple requirement calls for a larger capacitance. Capacitor ESR and ESL also affect performance, especially at high frequencies. If the LC filter is placed at the output of a switching regulator, the designer must also consider how the pole and zero created by the LC network affect the stability of the negative feedback control loop.
How Can Signal Integrity and EMI Be Balanced When Defining Standards?
Signal integrity and EMC standards are still in draft form and are not publicly available. Balancing signal integrity and EMI is not a matter for test specifications. The best way to achieve balance would be to reduce communication speed, but this approach is not generally accepted.
How Can a PCB Meet EMC Requirements Without Excessive Cost Pressure?
The EMC-related cost of a PCB usually comes from adding ground layers to improve shielding and from adding ferrite beads, chokes, and similar components to suppress high-frequency harmonics. In most cases, mechanical shielding is also needed for the complete system to pass EMC requirements. Several PCB design techniques can reduce the electromagnetic radiation produced by the circuit.
First, choose devices with slower slew rates where possible. Slower edges contain less high-frequency energy, so the signal produces less high-frequency content. Second, place high-frequency devices away from external connectors. Third, maintain impedance matching for high-speed signals, and pay attention to routing layers and return current paths. This reduces high-frequency reflection and radiation. Fourth, place sufficient and appropriate decoupling capacitors at each device power pin to smooth noise on the power and ground planes. Verify that the capacitor frequency response and temperature characteristics meet the design needs. Fifth, near external connectors, split the ground appropriately and connect the connector ground to chassis ground nearby. Sixth, use ground guard or shunt traces beside selected very high-speed signals, but account for their effect on trace characteristic impedance. Seventh, inset the power plane 20H from the ground plane, where H is the distance between the power plane and the ground plane.
Why Are Digital and Analog Grounds Usually Separated on Boards with Multiple Digital and Analog Blocks?
Digital circuits create noise on the power and ground planes when they switch between high and low levels. The magnitude of this noise depends on signal speed and current. If the ground plane is not split and the digital noise is large while the analog circuits are close, the analog signals can still be disturbed by ground noise even when digital and analog signals do not cross. In other words, a non-split ground plane can be used only when the analog circuit area is far enough from the digital circuit area that generates large noise. Separating the grounds limits the spread of digital noise into the analog region.
What Should High-Speed PCB Designers Consider When Applying EMC and EMI Rules?
EMI and EMC design must consider both radiated and conducted emissions. Radiated emissions are associated with higher frequencies, typically above 30 MHz. Conducted emissions are associated with lower frequencies, typically below 30 MHz. A design should not focus only on high frequencies and ignore low-frequency behavior. A good EMI and EMC design considers device placement, PCB stackup, routing of important connections, and device selection from the start of layout. If these factors are not arranged well in advance, later fixes will be less effective and more costly.
For example, place clock generators away from external connectors. Route high-speed signals on inner layers where possible, and pay attention to impedance matching and continuous reference planes to reduce reflections. Choose devices whose output slew rate is as low as possible to reduce high-frequency content. Select decoupling and bypass capacitors whose frequency response meets the need to reduce power plane noise. Also pay attention to the return path of high-frequency signal currents so that the loop area, and therefore the loop impedance, is as small as possible to reduce radiation. Split ground planes can be used to control the range of high-frequency noise. Finally, choose PCB-to-chassis ground connection points appropriately.
How Can Stackup Arrangement Reduce EMI?
EMI must be considered at the system level. A PCB alone cannot solve the problem. For EMI, the main role of the stackup is to provide the shortest return path for signals, reduce coupling area, and suppress differential-mode interference. In addition, tight coupling between the ground plane and the power plane, with the ground plane extending somewhat beyond the power plane, helps suppress common-mode interference.
Why Is Copper Pouring Used in PCB Design?
Copper pouring is used for several reasons. First, for EMC: a large-area ground or power copper pour provides shielding, and special grounds such as PGND provide protection. Second, for PCB process requirements: copper is poured on layers with sparse routing to ensure plating quality or prevent lamination deformation. Third, for signal integrity: a complete return path is provided for high-frequency digital signals, and routing for the DC network is reduced. Copper pouring may also be used for heat dissipation and for special component mounting requirements.
Related Reading:
EMC Engineer Skills and Common Components: Chokes, Ferrite Beads, Filter Capacitors
EMC Design Principles and EMI/EMC Questions for PCB Engineers
FCC and EMC Compliance Requirements Explained for PCB Design
Ferrite Beads vs. Inductors for High-Frequency Filtering on PCBs
Class-D Amplifier PCB Routing: EMC, Power, and ESD Essentials
EMC Fundamentals: Disturbance and Interference Control Terms
EMC Measurement, Equipment Classification, and Transceiver Terms
Power Control, Supply Impedance, and Flicker Terminology Explained
Internal EMC Design and PCB Layout Techniques for Electronic Products
