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Mixed-Signal PCB Layout and Routing Design

Author : Alex Chen | PCB Design & High-Speed Engineering Specialist

September 18, 2026


Mixed-signal boards must keep analog and digital domains from coupling into each other, control return paths, and preserve both signal integrity and power integrity. The guidelines below are field-proven practices for achieving that separation in placement, routing, and grounding.

 

Prioritize Analog Layout and Partition the Domains

When a design includes both analog and digital circuits, prioritize the layout and routing of the analog sections. Optimize placement, routing, and grounding first for the sensitive analog nodes so that digital noise has less opportunity to couple into them and so that the analog circuits themselves are less susceptible to that noise.

Before placement, analyze and partition the digital and analog circuits. Place digital devices and analog devices in distinct functional regions. Whether to split analog ground (AGND) and digital ground (DGND) should follow the relevant device datasheet and the schematic. Many modern ADC reference designs use a unified digital ground, yet the PCB layout should still enforce functional partitioning to reduce interference. In mixed-signal sections that use ADC or DAC devices, the split line often aligns with the device's pinout. Consult the datasheet and classify each signal accordingly so that analog pins remain on the analog side of the partition and digital pins remain on the digital side.

Example of mixed-signal placement partitions

Analog and digital region separation example

Analog devices are often placed near the board edge so that they align with analog interface connectors. If the customer has not specified the analog connector locations, keep analog interfaces away from power connectors and from digital interfaces such as UART, Ethernet, and HDMI. Separate analog receive and transmit connectors from each other so that the return currents and the radiated fields of one do not land directly on the other.

 Analog connectors placed near board edge and separated from digital interfaces

Handle Ground and Power Splits Carefully

If the schematic separates AGND and DGND, maintain that separation on all layers for both signal and power routing. Avoid crossing a ground split with any signal or power trace. A crossing forces the return current to detour around the gap, enlarging the loop and creating a discontinuity that couples noise between domains. Power rails should also avoid crossing splits. If a power rail must cross, use a ferrite bead or a Pi filter to connect across the boundary so that the high-frequency content is attenuated. Keep the split gap at least 20 mil.

Ground and power split layout example

If isolation is implemented only by adding ferrite beads in the power rails, the power return path can become long. Add a second ferrite bead bridging AGND and DGND near the analog power bead. This provides a controlled, local return path for the analog and digital power currents instead of forcing those currents to travel the length of the board to find a common point.

When a single signal must cross a split, a ferrite bead or a 0 Ω jumper can be added in series to control the crossing. For multiple signals that must cross, concentrate the digital lines and provide a single controlled bridging point. A single bridge keeps the return current localized and prevents a scattered set of crossings from re-coupling the two domains.

Single-point bridging for multiple digital signals across a split

 

Place Components According to Signal Flow

Plan placement according to signal flow. Arrange small analog signals first—typically the low-level inputs arriving from interfaces—then large analog signals after amplification or at the ADC, and finally the digital signals associated with an FPGA, DSP, or CPU. This order supports short, clean paths and simplifies return-path control because each stage stays inside its own region.

Signal-flow-oriented placement from small analog to digital domain

Place the A/D converter so that it straddles the analog and digital partitions. Typically, AGND and DGND are tied together at the ADC according to the datasheet guidance. The single connection at the conversion boundary gives the conversion currents a controlled return path and prevents those currents from circulating through the rest of the ground system.

Signal-flow-oriented placement from small analog to digital domain

Common analog devices and signals that require this treatment include RGB video signals; IF inputs via BNC or SMA connectors; audio and microphone circuits; op-amps, comparators, and filters; infrared and thermal sensors; Bluetooth-related sensors; crystals; and RF antennas and RF switches. Treat these as analog or RF-critical circuits and keep them separated from noisy digital sections.

 

Power Routing and Decoupling for Analog Devices

Follow the schematic functional order during placement and routing. For analog device power pins, place both bulk and high-frequency decoupling capacitors. Prefer routing the power through the capacitors before it reaches the device pins so that the high-frequency current loop remains local to the pin. Use at least 20 mil width for analog power traces. For fine-pitch pins, match the escape trace width to the pin width until the trace reaches the decoupling capacitor or via; after that point the trace can widen to the 20 mil minimum.

Power decoupling topology for analog devices

Recommended analog power routing to decoupling capacitors

Where space permits, guard sensitive analog traces with grounded shielding—either guard traces or a ground pour. Add stitching vias along the guard at intervals not less than 200 mil so that the guard remains a low-impedance connection to the reference plane. Without periodic stitching, a long guard can itself become a coupled structure.

 Guarded analog trace with ground stitching vias

Analog Signal Routing Practices

Avoid vias in analog signal paths where possible, and use trace widths above 10 mil. For 50 Ω analog lines, ensure a continuous reference plane (inter-layer referencing) and avoid stubs. A stub or a broken reference plane introduces an impedance discontinuity that reflects energy back toward the source. Route the signal through protection components, such as ESD devices, before it exits to connectors or long runs so that the protection acts at the boundary rather than after the trace has already entered the board.

Keep switching power regulators, clock circuits, and high-power components away from analog circuits and sensitive analog traces. The magnetic and electric fields from these sources couple readily into high-impedance or low-level analog nodes.

For baluns (balanced-to-unbalanced converters), control the input and output impedance according to the design. Follow the schematic for the ground configuration on both sides of the balun. In most cases there is no ground split at the balun; the grounds are continuous so that the balanced and unbalanced sides share a common reference.

 

Specific Signal Classes

For RGB signals, increase the line width to more than 10 mil and provide ground shielding. When these signals must cross a split, adding ferrite beads is generally recommended. For BNC or SMA signal pins, clear copper on all layers beneath the pins, with a clearance of at least 20 mil from the pad. This prevents the connector pin from seeing a nearby copper edge that would alter its impedance or couple noise. Route audio left and right channels with 10 mil width and 10 mil spacing; apply the same width and spacing to MIC+ and MIC−.

RGB, BNC/SMA, and audio routing examples with ground shielding and clearances

Op-amps, comparators, and filters typically do not require controlled impedance. Use 10 mil trace widths and adopt a straight, linear "I-shaped" flow in overall placement and routing. The linear arrangement keeps the signal path short, maintains clarity, and minimizes coupling between stages.

IF routing with controlled impedance and antenna keepout example

For IF signals, use inter-layer referencing to achieve 50 Ω impedance while keeping traces as wide as possible to reduce attenuation. Under antennas, remove copper (copper keepout) and open the solder mask as required. Maintain a clearance region preferably greater than 5 mm so that the antenna is not loaded by nearby copper.

 

Digital Receive and Transmit Separation

Separate digital receive and transmit routing. Avoid placing Rx and Tx on the same layer when possible. If they must share a layer, maintain the 3W rule—spacing at least three times the trace width—between Tx–Tx pairs and between Rx–Rx pairs, and maintain the 5W rule between Rx and Tx lines. The wider spacing between the opposing directions reduces crosstalk that would otherwise fold transmit energy into the receive path.

3W/5W rule spacing for digital Rx/Tx routing

Taken together, these practices keep the analog domain quiet, give return currents a defined path, and prevent the digital and power sections from becoming the dominant noise source on the board.

Alex Chen | PCB Design & High-Speed Engineering Specialist Alex Chen | PCB Design & High-Speed Engineering Specialist

Alex Chen is a senior PCB design engineer with extensive experience in high-speed and high-density circuit design. He specializes in signal integrity, impedance control, and multilayer PCB layout optimization. At AIVON, he reviews and refines content related to PCB design principles, EDA tools, and advanced layout techniques. His expertise helps engineers avoid common design pitfalls and improve performance, reliability, and manufacturability in complex PCB projects.

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