PCB Design: A Sound Power Design Is Half the Battle

1. Organize the Power Requirements with a Power Tree

Power design should begin with a clear power tree developed from a systematic analysis of the board's power requirements.

The power analysis should identify the voltage range, current requirement, transient response, and power-up sequence for every supply rail. Clock-related requirements should also be documented separately, including the input logic standard, frequency, jitter, and timing sequence for each clock. Each pin must be assigned and connected correctly, and the logic levels at interconnected pins must satisfy the relevant requirements.

Device manufacturers typically provide power requirements for their own components. For example, an Intel device may specify coupling relationships and sequencing requirements between its power rails during startup.

The next question is how to implement these requirements on the actual board. Other components, such as network controllers and FPGAs, may also require complex power architectures and specific power-up or power-down sequences. In many designs, several devices use the same voltage rail. To simplify the architecture, a single supply output is often used to power all devices that require the same voltage. For example, one 3.3 V output may supply every component that uses 3.3 V.

This approach couples the requirements of all connected loads. The design must therefore account for the current demand, transient behavior, and sequencing requirements of every device connected to the shared rail.

A practical workflow is to first list the power requirements of all devices and then consolidate common requirements. This produces the complete board-level power requirement and the required power-up sequence.

Based on these requirements, the complete power architecture can be developed. The designer should select a power solution that provides a reasonable balance between functionality, reliability, and cost. A functional block diagram should be created first and reviewed before detailed schematic and PCB implementation begins.

Key Charts and Documents

• Power requirement analysis table: Lists the power requirements of every device, including voltage range, current demand, transient response, and power-up sequence.
• Common-requirement consolidation diagram: Shows how the power requirements of devices using the same voltage are combined.
• Board-level power architecture block diagram: Shows the power architecture, including each power module and the connections between modules.
• Power-up timing diagram: Defines the startup order and timing requirements of each power module so that all connected devices receive power within their required limits.

Once these documents are complete, the power-design requirements for the board are clearly defined.

2. Plan the Power-Module Layout from the Input and Output Requirements

The power input is generally provided as a DC source from a backplane, adapter, PoE interface, USB connection, or similar source. A board may have one input or several inputs that are combined through an appropriate power-path design.

The power outputs are the voltage rails identified and consolidated during the power-requirement analysis. The approximate locations of the loads should then be considered together with the location of the power modules.

Component placement is affected by many factors, including routing, thermal management, mechanical structure, and electromagnetic interference. After these factors have been considered, particular attention should be paid to the location of the high-current power rails for the main processor and other high-power devices, such as DDR memory.

The power-pin distribution of the main processor should be reviewed first. This distribution determines how the critical power planes should be allocated and how each supply rail will reach the processor. During this current-delivery path, the following principles should be followed:

1. Minimize coupling between power planes and prevent unrelated power planes from becoming unnecessarily interwoven.
2. Use the shortest practical current path and avoid unnecessary detours.
3. Minimize layer transitions.
4. Use complete power planes for critical supply rails whenever the stackup and placement allow it.

For this reason, the power-flow direction should be planned before placing the DC/DC converters. The hardware designer should be able to visualize the complete power-delivery topology. The actual topology is often considerably more complex than a simplified diagram.

3. Do Not Route the Input Power Across the Entire Board

Keeping the input power path localized is a simple principle, but it is easily overlooked.

First, the input power comes from outside the board, so the interference it introduces may be difficult to control. Second, the input supply feeds each DC/DC converter, and the input capacitor of each converter is associated with relatively large and rapidly changing current. The area of this switching-current loop must be controlled.

Even when the high-current loop is carefully managed, the input supply and the DC/DC converter can still form a time-varying current loop. Because this loop has inductance, it can become a source of electromagnetic interference.

Both the red loop and the yellow loop shown in the design analysis should be controlled. The input power path should be kept short and localized rather than being routed across the board to reach multiple converter stages.

4. Place the Buck-Converter Input Capacitor Close to the Switching Devices

The high-frequency current loop shown in the switching-converter analysis should be made as small as possible.

The first step is to identify the high-frequency current loop for each topology. The dashed loop in the corresponding diagram represents a loop with a relatively large di/dt.

In a buck converter, the high-frequency current loop is formed by the input capacitor and the two switching devices, or by one switching device and one diode. In a boost converter, which is the dual topology, the high-frequency current loop is associated with the output capacitor and the two switching devices. In a SEPIC converter, the high-frequency current loop is formed by the two switching devices and the two capacitors.

These high-frequency loops are formed by the switching devices and the capacitors connected to them. The current changes most rapidly while the current is switching between the two switching devices. By contrast, the inductor current cannot change instantaneously, so the inductor limits di/dt and is not usually the primary part of the high-frequency switching loop under consideration.

After identifying the high-frequency loop, the next step is to suppress the near-field magnetic field generated by this noise source. The most effective method is to reduce the loop area. The current magnitude is normally determined by the required output power and cannot be reduced arbitrarily, so minimizing the physical loop area is the principal layout approach.

The placement of the input capacitor is especially important. In the illustrated comparison, placing the capacitor on the back side of the device reduces the distance to the switching devices. The measured noise is substantially lower than when the capacitor is placed beside the device or connected with relatively long leads.

As advanced packaging develops, more devices integrate input capacitors into the package or device structure. This can further reduce the high-frequency loop area and improve EMC performance.

When two devices, A and B, are tested with the same device type and the same PCB layout, the device with integrated capacitors produces lower high-frequency conducted noise in the CISPR 25 test range. This provides a significant advantage in conducted-emissions testing.

5. Place Decoupling Capacitors as Close as Possible to the Load

The purpose of a decoupling capacitor must be understood before its placement is determined. At the load, the objective is to maintain good power quality and reduce noise across the complete power-distribution network.

Noise in a power system can come from several sources. The output voltage of a regulator is not perfectly constant and contains ripple. In addition, the regulator cannot respond instantaneously to rapid changes in load current. The effective response bandwidth of a regulator is generally within approximately 200 kHz in the context discussed here. Beyond this range, a voltage drop may appear at the regulator output pins when the load changes rapidly.

Transient load current also produces voltage drops across the impedance of the power path and the ground path. External interference can further degrade the supply voltage.

The transient load current mentioned here is not generated by the regulator output stage itself. It is caused by changes in the load, which result from large numbers of digital signals switching. An integrated circuit contains a large number of logic gates. Its basic output cell can be represented as a CMOS inverter.

When the control signal is low, the PMOS transistor turns on and the output becomes high. At the instant of switching, VCC charges the input of device B through L_VCC and R. When the control signal is high, the NMOS transistor turns on and the output becomes low. The charge stored at the input of device B is then discharged through the NMOS transistor.

Whenever the output state of the CMOS inverter changes, the current through the circuit also changes. Voltage is therefore induced across the inductive elements in the trace, vias, power planes, package, bond wires, and device pins.

The nominal GND potential should be 0 V. However, the connections between the device and ground have inductance, so a voltage V_GND can be induced across those connections. The ground potential at the device is consequently raised above 0 V.

When multiple CMOS outputs switch from low to high at the same time, negative-voltage noise can be observed on VCC. The disturbance also affects GND and may produce oscillation. When the outputs switch from high to low, positive-voltage noise can be observed on GND, while VCC is also affected and may exhibit oscillation.

A single CMOS circuit can create this type of disturbance. When a large number of CMOS circuits operate simultaneously, the resulting interference on the power and ground planes can become significant. As device pin counts, current demand, and integration density increase, power integrity becomes increasingly important.

1. As integration density increases, the number of transistors inside the device also increases. These transistors form internal gate circuits, combinational logic, delay lines, state machines, and other logic structures.
2. The external power pins provide a common power node for the internal transistors. When transistor states change, power noise is inevitably coupled through the device.
3. The internal transistors operate with internal or external clocks. Because of internal propagation delay and device-to-device timing differences, the transistors cannot change state at exactly the same time. Some gates may complete a transition while others are still switching, allowing power noise from one group of gates to reach the inputs of other gates.

This explains why decoupling capacitors should be placed close to the power pins of the powered device.

A decoupling capacitor provides a short-duration, high-frequency response for the power system. It supplies local transient current and helps maintain a stable voltage at an integrated circuit or other load.

1. Reduced inductive effects: Power and ground connections contain inductance. When a load suddenly requires a large current, this inductance produces a voltage drop. A nearby decoupling capacitor supplies the transient current locally and helps counteract the voltage drop.
2. Lower power-loop impedance: A decoupling capacitor has relatively low impedance at high frequencies. Placing it close to the load reduces the total impedance of the power loop and makes high-frequency transient current easier to deliver.
3. Reduced propagation of voltage fluctuations: Voltage disturbances on a power rail propagate along the interconnect. A nearby capacitor reduces the distance over which the disturbance must travel before local energy is supplied to the load.
4. Reduced noise coupling to adjacent circuits: The capacitor absorbs part of the noise on the local power path, limiting the amount of noise that propagates through the power network to nearby circuits.

Small-package, low-value decoupling capacitors should be placed especially close to the power pins because they are intended to provide high-frequency response and rapid current delivery. Their smaller physical dimensions generally help reduce parasitic inductance, allowing them to respond more effectively to fast transient current demands.

• High-frequency response: Small-package and low-value capacitors are typically effective over higher-frequency ranges. Their smaller physical dimensions help reduce the influence of parasitic inductance on high-frequency impedance.
• Rapid current transfer: Small packages generally have lower equivalent inductance, allowing current to be delivered more quickly. Shortening the path between the capacitor and the power pin further reduces the inductance of the transient-current path.
• Local noise suppression: Low-value capacitors are mainly used to handle local, short-duration, high-frequency noise. Placing them at the power pins provides immediate decoupling where the supply enters the device and limits the disturbance seen by the rest of the board.

When a capacitor is connected to the power and ground planes through vias, the connection from the pad should be kept short. The current loop can be represented as:

Power plane → via → short trace → capacitor pad → capacitor → capacitor pad → short trace → via → ground plane.

The basic rule for via placement is to minimize the area of this loop and therefore reduce parasitic inductance.

• Long traces from the pads to the vias: This creates a large loop area and introduces significant parasitic inductance. This method should be avoided.
• Vias at both ends of the capacitor pads: This produces a much smaller loop area and lower parasitic inductance than the first method. It can be acceptable when space is limited.
• Vias beside the pads: This further reduces the loop area and parasitic inductance and is a better placement method.
• Multiple vias beside both pads: Each terminal of the capacitor is connected to the power or ground plane through parallel vias. This reduces parasitic inductance even further and should be used when sufficient space is available.
• Via-in-pad: Drilling directly in the pad provides the smallest parasitic inductance. However, the PCB must use a suitable filled-via process; otherwise, solder may flow into the via during assembly and cause soldering defects.

Good power design begins with a complete understanding of the power tree and continues through power-module placement, current-loop control, converter layout, and load-side decoupling. The central objective is to provide each device with a low-impedance, low-noise power path while preventing switching currents and transient load currents from spreading unnecessarily across the board.