DisplayPort 1.4 PCB Layout Guidelines for BGA Fan-Out and Connector Routing
DisplayPort (DP) is the display interface published by VESA. In addition to video, DisplayPort supports high-definition audio and enables higher resolution and refresh rate than earlier consumer display links of comparable pin count. The DP 1.4 port specification is based on DP 1.3. Lane width is unchanged. Display Stream Compression (DSC), forward error correction (FEC), and high-dynamic-range (HDR) packets are added.
Because the physical lane width does not increase, the extra capability of DP 1.4 is carried on the same high-speed differential pairs. Layout quality therefore becomes more important, not less. Ground continuity around the BGA fan-out, intra-pair length control, and connector-region reference management determine whether those pairs remain usable at the rates where the new compression, FEC, and HDR features are actually used.
The guidelines below cover two regions that dominate DisplayPort signal integrity on a typical PCB: the BGA breakout and the DP connector footprint. When the connector operates at 8 Gbps or above, the connector-side rules are mandatory design inputs rather than optional polish.
Ground Vias and Ground Fencing in the DP BGA Region
Add ground vias in the BGA region at the locations shown in Figure 1-1 (a). Apply ground fencing as shown in Figure 1-1 (b). L is the ground-via pitch on the fence. D is the air gap between the fence and the signal. D ≥ 4 × W is recommended, where W is the signal trace width.
Figure 1-1 (a) | DP BGA region fan-out
Figure 1-1 (b) | Recommended ground fencing
Ground vias in the BGA field serve two purposes. They stitch the reference planes so return current can change layers with the signal, and they form a local fence that limits coupling between adjacent high-speed pairs. A DisplayPort breakout that leaves large unstitched gaps around the differential pairs forces return current to detour. That detour increases loop inductance, weakens isolation between lanes, and makes the pair more sensitive to nearby aggressors.
Ground fencing is the controlled version of that stitching. The fence vias are placed along the pair with pitch L and held a clearance D away from the signal. The recommended floor of D ≥ 4 × W keeps the fence far enough from the pair that it does not become an unintended impedance discontinuity, while still remaining close enough to provide a continuous return wall. If D is too small, the ground copper loads the pair and drops impedance. If D is too large, or if L becomes sparse, the fence stops acting as a fence and the pair is again routed through an open field.
Fan-out geometry should keep each DP pair over a continuous ground reference as it leaves the BGA. Layer transitions should occur with ground vias immediately adjacent to the signal vias so the return path follows the pair. The fencing pattern in Figure 1-1 (b) is intended to be applied along that escape, not only as a decorative via ring at the package outline.
Intra-Pair Length Matching
Hold intra-pair length mismatch to 6 mil. Apply length matching as shown in Figure 1-2.
Figure 1-2 | Intra-pair length-matching rules
Intra-pair mismatch is the length difference between the true and complement nets of one differential pair. That difference converts to intra-pair skew. At DisplayPort rates, even a small skew moves energy out of the differential mode and into the common mode. Common-mode current then radiates more readily and is more easily converted back to differential noise at the next discontinuity.
A 6 mil intra-pair budget is tight enough to keep that conversion under control on a typical board while remaining achievable with localized accordion or sawtooth matching. Matching should be applied near the region that created the mismatch, package escape, layer change, or connector entry, rather than collected as one large compensation structure far from the source of the error. Matching far from the discontinuity leaves a long unmatched segment in between, which is exactly the segment that generates common mode.
Inter-pair lane-to-lane matching is a separate budget and is not a substitute for the 6 mil intra-pair rule. A pair that is matched to other lanes but internally skewed still fails as a differential link.
Connector Rules at 8 Gbps and Above
When the DP connector operates at 8 Gbps or above, follow the connector recommendations below. DP 1.4 does not widen the lane, so higher effective payload is obtained by running the existing pairs harder and by relying on DSC, FEC, and HDR packetization. The connector footprint is then a first-order discontinuity in the channel. Layout around that footprint must preserve reference continuity, pair geometry, and ground via density.
Exit path and adjacent ground
Exit traces from the center of the connector footprint. Routing out of the center shortens the uncoupled pad region and keeps both members of the pair in a more symmetric environment as they leave the connector. Escaping from one edge of the footprint often forces one member of the pair through a longer pad stub or a more broken reference than the other member.
If one side of a high-speed signal in the connector is not next to a GND pin, add a GND via beside that signal in the layout. Connector pin maps are not always alternating signal-ground. A high-speed pin that lacks an immediate ground neighbor has a weaker local return. A ground via placed beside that signal restores a nearby return and reduces the isolated-pin discontinuity that would otherwise appear at the launch.
Connector selection
If the interface data rate is 8 Gbps or higher, the connector must meet the matching standard for that class of high-speed interface, for example HDMI 2.1, DP 1.4, or PCI Express 3.0. Recommended connector vendors include Molex, Amphenol, and HRS.
The point of the matching-standard requirement is mechanical and electrical consistency at the launch: pin geometry, ground-lead inductance, and the way the connector presents pads to the PCB. A connector that is electrically adequate at lower rates can still be the limiting discontinuity once the lane reaches 8 Gbps and above. Vendor selection does not replace layout control, but it sets a floor on the component that the layout then has to finish.
Reference voids and skip-layer grounding
Void one or two ground planes under the interface, depending on the connector. Connector surface pads sit over a stack-up that would otherwise place a ground plane immediately beneath a wide pad. That close ground can pull pad capacitance too high and drop the local impedance below the 100 Ω differential target used for HDMI and DisplayPort.
If L2 under the connector pads is voided, the reference must skip a layer and L3 must be the ground reference. If both L2 and L3 ground references are voided, L4 must be a ground plane and serve as the skip-layer reference. The pair is then referenced to the nearest remaining solid ground, not left over a fragmented or missing return.
Void size must be set from the connector part number and confirmed by simulation on the actual stack-up after that stack is locked for HDMI / DP 100 Ω. A void copied from another connector, or from a different dielectric thickness, will not automatically produce the same impedance. Reference void sizes based on an EVB first-order HDI stack-up can be used as a starting point, but they are not a substitute for simulation on the production stack-up.
Skip-layer referencing only works if the new reference plane is continuous under the launch and is stitched with ground vias at the void boundary. A void without a defined next-layer ground simply removes the return. A void with a well-stitched skip-layer ground is an impedance-tuning feature.
Ground vias on connector ground pads
Place two ground vias on each connector ground pad, as close to the pad as possible. A single via leaves more inductance in the ground lead and gives the return current only one path off the pad. Two vias in parallel lower that inductance and keep the ground pin from becoming a narrow bottleneck at the moment the high-speed pair launches into the board.
Via placement should hug the pad. A ground via that is electrically assigned to the pad but placed several millimeters away no longer belongs to the launch. The return current will already have spread or coupled before it reaches that via.
Recommended Connector Routing
Figure 1-3 | DP connector routing
Recommended connector routing combines the rules above into one launch geometry: pairs leaving from the center of the footprint, local ground vias beside high-speed pins that lack a ground neighbor, controlled voids under the pads with a defined skip-layer reference, and two ground vias on every connector ground pad. Intra-pair matching to 6 mil continues through this region so the connector does not consume the entire skew budget.
DisplayPort 1.4 keeps the same lane width as DP 1.3 and adds DSC, FEC, and HDR packets on top of that physical channel. The BGA fence, the 6 mil intra-pair rule, and the 8 Gbps connector treatment are how that unchanged lane width stays electrically usable. Layout that ignores ground fencing, skip-layer reference, or connector via density leaves the extra protocol capability sitting on a channel that can no longer support it.
