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PCB Layout and Routing Requirements for a PCIe Interface

Author : Alex Chen | PCB Design & High-Speed Engineering Specialist

September 08, 2026


PCI Express, abbreviated as PCIe, is a high-speed serial computer expansion bus standard. PCIe is a high-speed serial, point-to-point, dual-simplex, high-bandwidth interconnect. Each connected device is assigned dedicated lane bandwidth and does not share bus bandwidth. Its main advantage is a high data-transfer rate.

 

Main Differences Between PCIe 2.0 and PCIe 3.0

1. Maximum data rate

PCIe 2.0 provides a maximum data rate of only 5 GT/s, while the PCIe 3.0 data rate reaches 8 GT/s, which increases bus bandwidth. The PCIe 3.0 specification raises the data rate to 8 GT/s and remains backward compatible with PCIe 2.x/1.x, continuing to support the 2.5 GT/s and 5 GT/s signaling schemes.

2. Encoding method

PCIe 3.0 operates at 8 GT/s and drops the traditional 8b/10b encoding. It introduces several techniques, including enhanced signaling, data integrity, transmitter and receiver equalization, PLL improvements, clock-and-data recovery, and common extensions.

Because PCIe 2.0 and PCIe 3.0 have different characteristics, they also have different PCB design requirements.

 

PCIe Interface PCB Design Notes

Ground vias are recommended at the following locations in the BGA region. Differential signals should also be ground-guarded, with ground-via spacing on the guard traces less than 300 mil, as shown in Figure 1.

PCIe 3.0 BGA region fan-out routing with ground vias and guarded differential pairs

Alex Chen | PCB Design & High-Speed Engineering Specialist Alex Chen | PCB Design & High-Speed Engineering Specialist

Alex Chen is a senior PCB design engineer with extensive experience in high-speed and high-density circuit design. He specializes in signal integrity, impedance control, and multilayer PCB layout optimization. At AIVON, he reviews and refines content related to PCB design principles, EDA tools, and advanced layout techniques. His expertise helps engineers avoid common design pitfalls and improve performance, reliability, and manufacturability in complex PCB projects.

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