PCI Express (PCIe) is a high-speed serial computer expansion bus standard used to connect processors, graphics cards, storage devices, network adapters, and other peripheral hardware. Unlike traditional shared-bus architectures, PCIe uses point-to-point, full-duplex serial links. Each connected device communicates through a dedicated link, allowing data to travel in both directions simultaneously.
PCIe is widely used in modern computers, embedded systems, industrial equipment, and high-performance electronic devices. Its high data transfer rate makes it suitable for applications that require fast communication between processors, memory systems, storage, and peripheral devices. Higher-speed PCIe interfaces also introduce stricter PCB design requirements. The routing of differential pairs, impedance control, via transitions, return paths, and signal integrity can all affect link performance.
This article compares PCIe 2.0 and PCIe 3.0 and explains the key PCB layout and routing considerations for reliable PCIe interfaces.
What Is PCI Express?
PCI Express is a high-speed serial interconnect standard designed for communication between a host processor and peripheral devices. It uses differential signaling, in which each signal is transmitted through a pair of conductors carrying complementary electrical signals. The differential pair rejects common-mode noise and provides a well-defined transmission-line environment when the pair is routed with controlled impedance and a continuous reference plane.
A PCIe link consists of one or more lanes. Each lane includes one differential pair for transmission (TX) and one differential pair for reception (RX). Because PCIe supports full-duplex communication, the transmit and receive paths can operate simultaneously. The physical separation of TX and RX pairs also means that the board designer must treat the two directions as independent high-speed channels that still share the same ground reference and the same connector or package footprint.
PCIe Link Width
PCIe links are commonly described using lane widths such as x1, x4, x8, and x16. Each additional lane increases the aggregate bandwidth of the link. However, the actual bandwidth depends on the PCIe generation, encoding scheme, implementation, and negotiated link width. A wider link does not automatically deliver higher per-lane performance; it simply multiplies the number of independent differential pairs that must be routed and length-matched.
| PCIe Link | Number of Lanes | Typical Application |
|---|---|---|
| PCIe x1 | 1 | Network cards, expansion controllers |
| PCIe x4 | 4 | NVMe SSDs, storage controllers |
| PCIe x8 | 8 | High-performance adapters |
| PCIe x16 | 16 | Graphics cards and accelerator cards |
From a PCB standpoint, moving from x1 to x16 multiplies the number of differential pairs that must escape a package, maintain consistent impedance, and share a quiet return path. The routing channel, via density, and ground-stitching strategy all scale with the lane count.
Differences Between PCIe 2.0 and PCIe 3.0
PCIe 2.0 and PCIe 3.0 differ in several important ways, and each revision imposes different PCB design requirements.
Maximum data rate
PCIe 2.0 supports a maximum data rate of 5 GT/s, whereas PCIe 3.0 increases the data rate to 8 GT/s, raising overall bus bandwidth. The PCIe 3.0 specification increases signaling to 8 GT/s while maintaining backward compatibility with 2.5 GT/s and 5 GT/s link speeds. A link that negotiates down to a lower rate must still be routed so that it can also operate at the higher rate when both ends support it. The edge rate and the frequency content of an 8 GT/s signal are substantially higher than those of a 5 GT/s signal, so discontinuities that were tolerable at PCIe 2.0 become more visible at PCIe 3.0.
Encoding and signaling
PCIe 3.0 operates at 8 GT/s and departs from the legacy 8b/10b encoding. It introduces enhanced signaling techniques and improvements in data integrity, transmit/receive equalization, PLL performance, clock-data recovery, and other extensions to support higher data rates. The change in encoding means that the raw symbol rate more closely tracks the useful data rate, and the receiver relies more heavily on equalization to recover the eye. On the board, that dependence translates into a tighter requirement for a clean differential launch, a continuous reference plane, and controlled via transitions. Any impedance discontinuity or return-path gap that closes the eye must be compensated by the equalization, reducing the margin that remains for the rest of the channel.
PCB Design Considerations for PCIe Interfaces
Based on the differing characteristics of PCIe 2.0 and PCIe 3.0, the PCB layout and routing practices should be adjusted accordingly. The higher rate of PCIe 3.0 leaves less margin for the discontinuities that are introduced at the package breakout, at layer transitions, and along the route to the connector.
For BGA breakout and device fanout, it is recommended to add ground vias around the BGA area at the indicated positions. Differential signals should be surrounded by stitched ground (ground shielding), and the spacing between ground vias in the shield should be less than 300 mil. The ground vias serve two purposes: they provide a low-inductance return path when the differential pair changes layers, and they form a fence that limits coupling between adjacent TX and RX pairs. A stitch spacing greater than 300 mil leaves gaps large enough for return current to detour and for fields to leak between pairs. Keeping the stitch tighter than 300 mil maintains a continuous shielding wall along the escape.
See the accompanying figure for an example of PCIe 3.0 BGA fanout routing. The figure illustrates the placement of the ground vias relative to the differential pairs as they leave the BGA field. The same principle applies at the connector end of the link: the pairs should exit with a continuous reference and with ground vias adjacent to any layer change so that the return current can follow the signal without a large loop.
Because PCIe 3.0 runs at 8 GT/s and relies on equalization and improved clock-data recovery, the board contribution to the channel must be minimized. That means maintaining the differential impedance through the fanout, avoiding stubs on the via transitions, and ensuring that the ground fence remains continuous from the BGA to the point where the pairs enter the main routing channel. A design that was acceptable for a 5 GT/s PCIe 2.0 link may require a tighter ground-via pitch and a more carefully managed breakout when the same physical lanes are expected to train at 8 GT/s.
The combination of higher data rate, a change away from 8b/10b encoding, and the need for equalization means that PCIe 3.0 PCB layout is not simply a faster version of a PCIe 2.0 layout. The differential pairs, the ground stitching around the BGA, and the return path at every transition must be treated as first-order design constraints if the link is to train reliably at the full 8 GT/s rate.
