A few years ago, an internet company began investing in hardware development and quickly realized that hardware development required substantial capital. Unlike software products, which can often be developed and simulated with a reasonably capable laptop—or, at most, a rented server—advanced hardware products cannot be created with nothing more than a multimeter. The challenge becomes even greater for data-center-class equipment.
An oscilloscope is often described as an engineer's "eyes." Engineers need those eyes to be good enough to reveal the actual waveform of every signal under test.
Bandwidth and sampling rate are the two primary specifications used to evaluate an oscilloscope. Other important parameters include memory depth, vertical resolution, system rise time, jitter, and noise floor. Advanced functions may also include trigger systems, de-embedding, frequency-domain conversion, protocol decoding, and bus analysis.
Why Sampling Rate Matters
This article focuses on sampling rate. In simple terms, an oscilloscope's sampling rate is the sampling rate of its analog-to-digital converter (ADC). The ADC converts the analog input waveform into a sequence of digital samples that the oscilloscope can store, process, and display.
Consider a camera trying to photograph a hummingbird flying at high speed, with its wings beating thousands of times per second. If the camera's frame rate is too low, it cannot capture the motion of the wings. The resulting image becomes a blur rather than a clear representation of the instantaneous movement.
The same principle applies to signal acquisition. In signal-integrity analysis, aliasing occurs when the sampling rate is too low relative to the highest frequency component of the signal. High-frequency information is incorrectly "folded" into a lower-frequency region and mixed with the original low-frequency content, causing waveform distortion.
To avoid aliasing, the Nyquist-Shannon sampling theorem requires the sampling frequency to be at least twice the highest signal frequency:
fs ≥ 2fmax
The samples must also be taken at uniform time intervals. In practical applications, however, engineers generally choose a higher sampling rate to capture signal amplitudes more accurately and preserve more spectral information.
For an oscilloscope, the ADC sampling rate determines whether the instrument can effectively "freeze" rapid changes in the input signal. If the sampling rate is insufficient, aliasing occurs and the displayed waveform no longer accurately represents the original signal.
The Physical Limitations of a Single ADC
Modern signals can have bandwidths of tens of gigahertz. At the same time, the physical sampling rate of an individual ADC is limited by factors such as power consumption, semiconductor process technology, noise, and clock jitter.
For example, a single ADC may be capable of operating at 10 GS/s, while an application may require an effective sampling rate of 100 GS/s. Increasing the speed of one ADC indefinitely is not a practical solution. The converter architecture, power budget, thermal design, clocking system, and achievable signal-to-noise performance all impose constraints.
This creates a fundamental design trade-off for oscilloscope manufacturers, particularly in high-end instruments. A higher sampling rate is desirable, but the speed of a single ADC cannot increase without limit. Higher resolution is also desirable, yet operating the ADC at an excessively high speed can cause noise and power consumption to rise significantly.
What Is Time-Interleaved Sampling?
One way to address this limitation is to use multiple lower-speed ADCs in parallel and stagger their sampling times. This architecture is known as time-interleaved sampling, or TIS.
The basic idea behind TIS is simple: if one ADC cannot handle all the required samples, multiple ADCs can take turns acquiring them. Each ADC operates at a lower individual rate, but the combined system produces a much higher effective sampling rate.
Assume that an oscilloscope contains four ADCs, each operating at 10 GS/s. The oscilloscope controls their timing so that the ADCs sample the same signal with a 0.1 ns interval between successive acquisition phases:
- ADC1 acquires the first sample.
- ADC2 acquires the second sample, delayed by 0.1 ns.
- ADC3 acquires the third sample, delayed by another 0.1 ns.
- ADC4 acquires the fourth sample.
This sequence repeats continuously. Together, the four ADCs effectively sample the same signal at 40 GS/s.
This is the essence of time interleaving: time offset combined with parallel acquisition produces a higher effective sampling rate. The ADCs divide the acquisition task among themselves, allowing the oscilloscope to capture faster waveform changes than any individual converter could handle alone.
How TIS Resolves the Sampling-Rate Trade-Off
In principle, a TIS architecture can address the conflict between sampling rate and converter performance through several coordinated functions:
- Multiple lower-speed, high-precision ADCs can maintain good dynamic range and resolution.
- Controlled timing offsets between the ADCs can produce a higher effective sampling rate.
- Digital post-processing can correct the offset, gain, phase, and clock-jitter errors of each channel.
- The corrected samples can be combined to reconstruct an ultrahigh-speed waveform.
The process can be compared to an orchestra. Each ADC performs its assigned part during a different time segment. Digital reconstruction then combines these segments into a complete signal waveform. The final result depends not only on the performance of each individual ADC, but also on how accurately the separate channels are synchronized and matched.
The Calibration Challenge
If the concept were as simple as connecting several ADCs in sequence, the problem would be easy to solve. In practice, the most difficult task is ensuring that the outputs of the individual ADCs connect seamlessly. The channels must work together without introducing discontinuities into the reconstructed waveform.
TIS must address several types of mismatch between ADC channels. Differences in channel gain can cause the waveform amplitude to rise or fall periodically as the system switches from one ADC to another. DC offset differences can introduce baseline errors. Phase mismatch and clock-timing errors can produce high-frequency distortion and aliasing artifacts.
These errors are especially significant at high input frequencies. Even a small timing difference can correspond to a meaningful phase error when the signal frequency is in the gigahertz range. As a result, the calibration algorithm must identify and correct the small differences between channels across the relevant frequency range.
In a TIS architecture, digital calibration effectively "trims" the individual sample streams so that offset, gain, phase, and timing errors do not become visible as periodic artifacts in the reconstructed waveform. Without accurate calibration, the theoretical increase in sampling rate could be accompanied by degraded signal quality, spurious tones, or waveform distortion.
Why TIS Is Important in High-End Oscilloscopes
Time-interleaved sampling allows multiple ADCs to cooperate in the time domain. In this way, a group of converters can exceed the sampling-rate limit of a single device while retaining the benefits of using lower-speed, high-precision ADC channels.
This architecture is one of the key technologies that makes oscilloscopes with effective sampling rates above 100 GS/s possible. Its operating principle is straightforward: divide the sampling task among multiple ADCs, offset their acquisition times, and digitally reconstruct the waveform. However, successful implementation requires precise clock distribution, stable timing relationships, channel matching, and sophisticated calibration.
TIS can therefore be viewed as a method of overcoming individual component limitations through coordinated system-level design. Multiple ADCs work together to "assemble" a waveform with a higher effective sampling rate than a single ADC can provide. The concept is simple, but achieving accurate results at high bandwidths is a demanding engineering task.
