A 50 Ω impedance coupon can look correct on the bare board, then the same net's TDR plateau drops after solder mask. Do not assume first that the fabricator etched the trace too narrow. On a surface microstrip, solder mask is not only a protective color layer over copper. It enters the electric field. The space above the trace was close to air. After coating, that space is dielectric. Effective dielectric constant rises, so characteristic impedance falls even when geometry is unchanged. What must be checked is whether simulation and coupon measurement both represent the finished board.
First Separate Surface Microstrip From Other Structures
On a surface microstrip, part of the electric field is in the laminate and part is above the trace. With bare copper, the upper dielectric is close to air. A stripline is enclosed by reference planes and dielectric above and below, so it is not equally sensitive to a surface coating. When finished impedance is low, the first step is not to change every trace width. Group the nets by structure. Only deviations tied to outer-layer microstrip, local coating, and local openings should send the solder-mask model to the front of the review.
Impedance depends on trace width, copper thickness, reference-plane distance, and dielectric properties. After solder mask is added, the largest change is not the DC resistance of the copper. It is the field distribution. A larger share of the electric field sits in higher-dielectric material, so propagation velocity and capacitance per unit length change and impedance is pulled down. The same mechanism explains why one solder-mask thickness does not shift wide traces, narrow traces, and coplanar structures by the same amount.
The coated cross-section must also be drawn clearly. Full coverage, coating only on the trace top, coating on both the top and the sidewalls, and local openings between differential traces all redistribute the field. If the solver has only a single generic solder-mask thickness and no real cross-section, a displayed 50 Ω may be 50 Ω only inside that model. Confirm the finished cross-section and solder-mask process with the fabricator before deciding which details the model must keep.
There Is No Single Fixed Solder-Mask Offset
Engineering notes often quote an impedance drop of "several ohms." That magnitude cannot be copied onto every board. The dielectric constant after cure, coating thickness on the trace top and sidewalls, stacked print passes, and whether a copper-open window sits beside the trace all change effective dielectric constant. Material parameters can also change with frequency, so a low-frequency TDR conversion and a high-speed band model must use a consistent material definition.
Finished trace width is another variable that is easy to mix in. Outer copper goes through pattern plating and etch, so the cross-section is often not an ideal rectangle. Top width, bottom width, and copper thickness together set impedance. If the simulation uses only the nominal width while production builds a compensated trapezoid, the solder-mask shift stacks on top of width and thickness error. Separate geometry error from the coating dielectric and run sensitivity sweeps on each.
Simulation, Fabrication, and Test Must Describe the Same State
When a 50 Ω requirement is sent to the fabricator, state whether the target is bare copper, after solder mask, or after a local opening. Most finished-board acceptance cares about the final usable state, so the coupon should use the same stackup, copper thickness, etch, and solder-mask flow as the target nets on the board. If the board traces are opened and the coupon is coated, or the board traces are coated and the coupon is opened, a passing coupon does not prove the real nets pass.
The coupon can include long straight test traces of several widths, with test pads, reference ground, and probe pitch that the instrument can contact repeatably. Its purpose is not to draw one extra 50 Ω line. It is to map the process onto a measurable object. When solder-mask thickness or material lot changes, keeping coated and opened segments on the same board makes it easier to see where the offset comes from than reading one final number.
Pin the Cause With One-Variable Comparisons
During debug, first hold stackup, copper thickness, and width fixed and compare the same structure in a "no solder-mask" model and a "with solder-mask" model. Then hold the solver settings fixed and sweep solder-mask thickness and dielectric constant. On the real panel, measure coated and opened segments at the same location with the same probes and calibration. If the simulation trend matches the measured trend, go back to a cross-section to confirm finished width and coating thickness.
Do not narrow every outer-layer trace across the board only to pull one coupon back to 50 Ω. Coplanar ground spacing, differential coupling, and connector transitions also move when width changes and can make another structure worse. First confirm whether the impedance offset appears in the same direction on all outer-layer structures. Then re-solve width in the field solver. Then have the fabricator review the change against manufacturable tolerance. That sequence keeps a cause-and-effect chain instead of hiding several variables behind one number.
The drop after solder mask is a change in the dielectric around a surface microstrip. It is not a sudden failure of the width rule. On the next revision, put the solder-mask layer into the solver first, then run the coupon through the full finished process and compare coated versus opened segments. Is the current 50 Ω acceptance value measured before solder mask, or on the finished board?
