In production we define over-etching as the condition where copper is removed beyond the designed track width, leaving traces narrower than the artwork and often with heavy undercut. Under-etching is the opposite—residual copper remains between features, producing tracks wider than nominal and potential bridges. CAM engineers flag both as FR4 PCB etching defects the moment the measured etch factor moves outside 2.5–3.5 or the final trace width deviates more than ±20 % from the compensated artwork. Most factories hold final outer-layer trace width to ±10–15 µm on standard 1/2 oz copper; anything beyond that range is either reworked or scrapped.
How Over-Etching and Under-Etching Differ on the Finished Board
Over-etching attacks the copper from the side walls after the dry film has already defined the top surface. The result is a trapezoidal cross-section with a narrow top and flared base that has been eaten away. Trace resistance rises, current-carrying capacity drops, and fine-pitch features can open completely. Under-etching leaves copper feet or entire residual islands between tracks. The measured width is larger than design, impedance falls, and adjacent conductors risk shorting. Both defects appear on the same panel when etch chemistry, conveyor speed or copper thickness is uneven across the surface.
Why Trace Width Changes So Quickly Once Etch Balance Is Lost
The etch rate on FR4 is highly sensitive to three process variables: etchant concentration (normally cupric chloride or alkaline ammonia), temperature, and dwell time. A 5 °C rise or a 10 % drop in conveyor speed can increase lateral etch by 15–20 µm on 18 µm copper. Dry-film adhesion also matters; if the resist foot is weak, the etchant undercuts faster and over-etching accelerates. On the under-etch side, depleted chemistry or low temperature simply fails to clear the copper in the designed spaces, leaving conductive residues that AOI later flags as shorts. Copper foil thickness variation from the laminate supplier adds another 5–8 µm of uncertainty that the etch line must absorb.
Inner layers see the same mechanisms but with less margin because the copper is thinner and the subsequent lamination step locks the geometry in place. Once the core is laminated, an over-etched inner trace cannot be recovered.
What Happens on the Line When These Defects Are Not Caught
Over-etched traces open during electrical test or, worse, survive test but fail under thermal cycling when the remaining copper neck fractures. Under-etched boards produce hard shorts or intermittent leakage that only appear after solder-mask cure or after the first reflow. Yield loss is immediate: panels with more than a few percent of over- or under-etched features are stripped and re-etched only if the copper is still thick enough; otherwise they are scrapped. Downstream, impedance-controlled nets drift outside tolerance, high-speed signals degrade, and fine-pitch BGA escape routes become unreliable. Customer returns for open circuits or mysterious shorts after assembly are the typical end result.
How Factories Control Etch Parameters and Recover Trace Geometry
The first control is etch compensation in CAM. We systematically enlarge the artwork traces by the expected lateral etch amount—typically 20–30 µm per side on outer layers for 1 oz copper—so the final width lands on target after the isotropic etch. Inner-layer compensation is smaller because the copper is thinner and the etch is more controlled. Etch factor (depth divided by lateral etch) is monitored on every shift; values below 2.5 trigger chemistry adjustment or conveyor slowdown.
On the line we run continuous titration of the etchant, keep temperature within ±1 °C, and measure panel-to-panel trace width with automatic optical measurement after the etch chamber. AOI is set to catch both narrow traces and residual copper. When a panel shows systematic over-etch we increase conveyor speed or dilute the chemistry; under-etch is corrected by slowing the conveyor or raising temperature within the safe window. For critical impedance jobs we add a first-article etch coupon that is micro-sectioned before the full lot is released.
DFM rules further reduce risk. Designers are asked to keep minimum trace and space above 75 µm on outer layers and 100 µm on inner layers for standard processes. Isolated fine traces are flagged because they etch faster than dense copper areas. Copper balancing and thieving are added so the etch load is uniform across the panel.
When the Factory Will Accept a Wider Etch Window
On thick copper (2 oz and above) used for power planes we sometimes tolerate ±25 µm width variation because the absolute current capacity remains adequate. Prototype lots under 20 pieces may ship with a measured etch-factor note if the customer confirms the design has sufficient margin on critical nets. Boards that only carry low-frequency digital signals can accept slightly over-etched traces provided no opens are present. In every case the trade-off is clear: a looser etch window reduces scrap but raises the chance of impedance drift or latent opens under thermal stress, so the customer must own the functional risk.
From the fabrication side the controlling levers remain accurate etch compensation, tight chemistry and speed control, and early AOI feedback. When those are managed, PCB over etching vs under etching stays inside process limits and FR4 PCB etching defects rarely escape into finished boards.
