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Custom PCB Behind the PV Pi: From a 100-Board Plan to Shipped Rev D

Author : Daniel Li | PCB Assembly & Electronics Application Engineer

August 28, 2026


Luke Ditria did not open his video with a victory lap. He opened it with a number he and Matt Walker had not budgeted. The PhotoVoltaic Pi is a Raspberry Pi HAT that charges a 12 V LiFePO4 pack from a solar panel and talks to the Pi over UART. They thought a hundred boards would make the campaign worthwhile. Backers asked for about five times that. By late April 2026 they had packed 514 units and ordered 570 so extras could absorb scrap.

They wanted a HAT that would keep a remote Pi alive: true MPPT at up to 10 A, a 12–50 V VOC window, an RTC wake, a watchdog, and a stout 5 V rail. That brief only becomes a product when copper, mask, and silk survive a mid-size run.

Five Hundred Boards the First Sketch Did Not Budget For

Snap it onto a 40-pin Pi. Plug the XT30 pigtails into a LiFePO4 pack and a panel. The STM32 arrives flashed. PV Pi Manager sets charge limits, a wake alarm, and a low-battery shutdown. UART on pins 14 and 15 is why clones and older Jetson Nano boards can ride the same 5 V pins.

PV Pi

The campaign cleared a hundred boards in two days. That overshoot paid for twenty extra Rev C prototypes, real loads, and a tester PCB Matt designed so every unit could be flashed and measured in about half a minute. AIVON built and assembled that tester.

PCB tester on work

Rev B launched the Kickstarter. Rev C was the freeze they wanted. Because five hundred people were waiting, they built twenty Rev C boards first, ran them, and only then cut Rev D — the revision that left Melbourne. The punch list was unglamorous and right: silk you can still read after HASL, a connector few backers would use for an external temperature probe, and layout tweaks so the charger behaved under load. Twenty leftovers hit the store after fulfillment and sold out in twelve hours.

Rec B-Rec C-Rec D

A 120 W panel and a PV Pi can put a day's 5 W Pi budget into the pack in a little over an hour. True MPPT on the BQ25756 is what makes that hour count. The PCB keeps the hunt honest: short current loops, ceramics on the charger pins, and XT30 shells that wet on the first pass.

BQ25756

What Stayed on the 2-Layer HAT Through Rev D

None of the revisions asked for HDI. The BQ25756 is a 36-pin, 5 × 6 mm VQFN on a 0.5 mm pitch.

Parameter

PV Pi product HAT (Rev D shipped)

Layers / material

2-layer FR-4

Thickness / copper

1.6 mm class, heavier copper in the charger path

Finish

Lead-free HASL or ENIG on first articles

Outline

Raspberry Pi HAT, stackable 40-pin

Power / control

BQ25756 true MPPT; STM32F103, RTC, watchdog, UART 14/15

Connectors

XT30 solar and battery; later 5 V and UART breakouts

The production-intent pass also picked up a 5 V JST, an external UART header, and an RTC backup footprint. Those additions eat silk and decide whether a 0.5 mm-pitch charger still has a dam the mask process can keep.

Why Rev C Was Not the Board They Mailed

A Kickstarter that 5×s is a gift and a trap. The gift is cash for a pilot. The trap is mailing Rev B silk. The extra twenty Rev C boards paid for silk that had drifted onto pads, a temperature-sensor connector almost nobody would populate, and proof that the fixture would catch a wrong sense resistor before a pack saw 10 A.

They test in-house on purpose. A mid-size run is the worst place to outsource programming. Each panel can mix copper, paste, and parts differently. The first failure mode should not appear in a field enclosure.

Silk is the item people laugh at until five hundred boards land. I have watched the same SMT shorts on a different stackup. On a thin 4-layer FR-4 module we reviewed — 0.8 mm, 418 × 38 mm — several IC gaps sat under 0.18 mm, which is where a green-mask dam stops being a dam.

The original IC pad-to-pad spacing is less than 0.18mm

CAM's answer was a gang opening the customer accepted, plus a flag that silk under about 0.75 mm high and 0.65 mm wide will blur. Rev D's silk pass is that conversation on a HAT. At 0.5 mm pitch, a dam between every BQ25756 pin is how you buy solder bridges after reflow.

A solder mask opening designed between the pads

How AIVON Custom PCB Let Rev D Leave the Bench

Luke and Matt already had the product idea. What they needed was copper that would not invent failures while they climbed from a hundred-board plan to a 570-board order. AIVON's job was not to redesign the PV Pi. It was to make the product HAT and Matt's tester board boring enough that a thirty-second script could be trusted, and that Rev D silk would still be silk after HASL.

AIVON-sponsored custom PCB

That starts with the stackup nobody should overbuy. Two-layer FR-4, 1.6 mm class, lead-free HASL unless the first article argues for ENIG, extra copper under the charger and the XT30 pair. Open every PTH the assembler or the pogo needs. Tent only where the Gerber and the order note agree. Stop the 5 V pour about 0.2 mm before a routed outline — 0.4 mm if the panel uses V-cut.

The mask-bridge conversation is the same one we run when a fine-pitch IC shows up on a first article. On that 0.8 mm 4-layer module the pads sat closer than the process could keep a dam. We opened the tight clusters and released the job. A 0.5 mm VQFN charger on a 2-layer HAT is a milder version of the same physics. Ask for a dam only where the gap can hold one. Gang-open the rest.

Panelization is the other half of custom once the campaign clears 500. Name holes past 3 mm as precision-routed. Put 0.8–1.0 mm mouse bites on the tabs. Then board 400 matches board 1.

What the boards enabled is specific. The tester could carry muxes and a programming header without probe pads vanishing under ink. The HAT could carry the charger, the STM32, and the XT30 pair without the 40-pin wandering off the pad. Sense parts stayed two-wire accessible so a wrong value dies in a second instead of on a roof. Once those details were in the copper, Luke was bagging standoffs while the next hundred boards were still in process.

Figure: STM32, 5V Output&UART Comms

DFM checklist for a Kickstarter-scale solar HAT

Check

Why it shows up on PV Pi

Pass look

Silk ≥0.75 mm high / 0.65 mm wide, off SMD pads

Rev D existed because earlier text did not survive HASL

Readable RefDes after finish

Pad-to-pad ≥0.18 mm where a mask dam is required

BQ25756 0.5 mm-pitch neighborhood

Dam intact, or a documented gang opening

Copper ≥0.2 mm from routed outline (≥0.4 mm if V-cut)

HAT outline plus XT30 shells

No 5 V pour on the router path

Quote tenting matches the mask layer

HASL will fill an open via

One rule in the fab notes

PTH vs NPTH named on header, standoffs, XT30

Wetting and clear barrels

Drill chart matches the pads

Unused connector removed before the production panel

Rev D dropped a temp-sensor port few would use

Assembly does not stuff an empty idea

In-house flash-and-measure before the courier

514 field units, not a hope

Script fails a board in ~30 s

Steal the silk row first. A 5× campaign will pay for a twenty-piece pilot, not five hundred boards with yesterday's text.

Ship the Revision You Can Stand Behind

AutoEcology's story is a remote-Pi brief that met a crowd. Luke and Matt kept the HAT on two layers, spent the extra Rev C boards on silk, and refused to treat testing as optional once the order book passed five hundred. AIVON's part was the dull copper: mask that matches the quote and panels that break clean.

If your own campaign just 5×d, freeze the stackup, spend a short pilot on the things that only show up at quantity, and put a fixture on the same FR-4 rules as the product. That is how a hundred-board idea becomes 514 packed HATs.

 

FAQ

Q1: How many PCB revisions should a Kickstarter HAT expect before shipping?

A1: Budget a production-intent rev, then a short pilot if demand jumps. PV Pi launched on Rev B, proved Rev C on twenty boards, and mailed Rev D.

Q2: Why bother fixing silkscreen on a 10 A power HAT?

A2: Operators stuff what they can read. Keep text off pads and above about 0.75 × 0.65 mm.

Q3: Can a 10 A MPPT Raspberry Pi HAT stay on 2-layer FR-4?

A3: Yes, if the charger path is poured and the VQFN thermal pad is real. Four layers do not fix a mask dam you cannot hold.

Q4: When should you gang-open pads instead of drawing a solder-mask bridge?

A4: When pad-to-pad drops under about 0.18 mm on standard green mask. A missing dam is a short after reflow.

Q5: Is factory programming enough on a 500-board run?

A5: Not if you still send a bed and an image. In-house flash catches the mix that changes every panel.

Q6: Should an unused connector stay on the production panel "just in case"?

A6: No. Rev D dropped the external temperature port. Empty footprints still need DFM.

Daniel Li | PCB Assembly & Electronics Application Engineer Daniel Li | PCB Assembly & Electronics Application Engineer

Daniel Li is an experienced PCB assembly and application engineer with over 10 years of experience in SMT and DIP processes. He focuses on soldering quality, stencil design, and defect analysis, as well as real-world PCB applications across industries such as automotive, industrial, and consumer electronics. At AIVON, he reviews and improves content related to assembly techniques and application scenarios, helping bridge the gap between design and manufacturing.

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