WLCSP Package Overview
Wafer-level chip-scale packaging (WLCSP) is a wafer-level packaging technology. Unlike conventional packaging, in which the wafer is first diced and the individual dies are then packaged and tested, WLCSP processing is performed on the complete wafer before dicing. The resulting package is therefore approximately the same size as the silicon die itself.
A WLCSP package consists of the silicon die, re-passivation layer, under-bump metallization (UBM), and solder balls or bumps. The solder balls are formed directly on the silicon die to bring the internal circuitry out to the PCB.
FCQFN Package Overview
Flip-chip quad flat no-lead packaging (FCQFN), also known as flip-chip packaging on a leadframe, is an advanced package technology developed from the QFN package. The active side of the die faces downward and connects directly to the terminals on the leadframe through bumps. The package also includes an exposed pad around the device for heat dissipation.
Compared with WLCSP, FCQFN offers several practical advantages:
- The resin surrounding the outside of the die provides better resistance to mechanical stress.
- FCQFN devices are easier to support during repair. WLCSP devices can be damaged if excessive or improperly applied force is used.
- An FCQFN device can generally be reused during repair, whereas a WLCSP device typically cannot be reworked for reuse.
- FCQFN devices provide improved package-level reliability in tests such as drop testing and bending testing.
- After testing, FCQFN devices can be taped and reeled directly. WLCSP devices normally undergo additional processes, including wafer thinning, marking, dicing, and taping. These additional operations create a small risk of damage and failure.
- The metal leadframe provides better thermal performance than the WLCSP structure.
Because WLCSP devices generally have higher production costs, CSP products may be made compatible with FCQFN packages to reduce cost. Semiconductor manufacturers can achieve this compatibility through the design of the leadframe, die, and package structure. At the application level, the key tasks are to develop compatible PCB pads and verify the SMT assembly process.
Compatible PCB Pad Design
The WLCSP device used in this evaluation was a port-protection switch with the package designation WLCSP 1.82 × 1.27-12B. Its pitch was 0.4 mm, the solder-ball diameter was 0.268 ± 0.020 mm, and the solder-ball height was 0.195 ± 0.020 mm.
The FCQFN device was an overvoltage-protection load switch from the same manufacturer. Its package designation was FCQFN 1.8 × 1.3-12, with a 0.4 mm pitch. The bottom pad diameter was approximately 0.25 mm, and the first-pin pad was square with a 0.25 mm chamfer.
Compatible WLCSP and FCQFN pads can use either a non-solder-mask-defined (NSMD) structure or a solder-mask-defined (SMD) structure. The evaluation used NSMD pads. The PCB pad diameter was approximately 0.23 mm, and the solder-mask opening was approximately 0.33 mm.
Using one PCB footprint for both packages simplifies layout management and avoids a board redesign when the package type changes. However, the footprint must accommodate the geometric differences between the solder balls of the WLCSP device and the leadframe terminals of the FCQFN device. The solder-mask opening and stencil aperture therefore need to be verified together with the pad dimensions rather than treated as independent parameters.
Compatible Stencil Design
For CSP or QFN devices with a 0.4 mm pitch, a typical stencil thickness is 0.08–0.10 mm, with aperture dimensions of approximately 0.23–0.24 mm. This evaluation used an FG nano-stencil with a thickness of 0.08 mm and aperture dimensions of approximately 0.24 mm, as shown in Figure 7.
Stencil thickness and aperture size directly affect solder-paste transfer, joint volume, placement tolerance, and the possibility of bridging. For a fine-pitch package, the aperture must provide sufficient paste volume while preserving adequate separation between adjacent deposits. The same stencil was used for both package types in this evaluation so that the comparison focused on the package and solder-joint differences rather than on different printing conditions.
Evaluation Plan
- Samples and parameters: 500 WLCSP devices and 500 FCQFN devices were assembled. Both used the same PCB design, including 0.23 mm pad diameters and an NSMD structure, as well as the same stencil with a thickness of 0.08 mm and 0.24 mm apertures. Placement and reflow parameters were the same as those used in the normal production project.
- Cross-section verification: Samples were taken after SMT placement and reflow for metallographic cross-section analysis. The solder-joint condition and stand-off height were examined.
- Reliability testing: After functional testing, 80 devices of each package type were subjected to 300 thermal-shock cycles and 1,000 temperature cycles.
- Post-reliability analysis: The samples were cross-sectioned again after reliability testing to determine whether the solder-joint structure had changed.
Assembly Quality Verification by X-Ray and Cross Section
X-Ray Inspection
Ten FCQFN devices and ten WLCSP devices were inspected by X-ray. No open solder joints or short circuits were found, and no devices had excessive voiding above 25%. Minor placement offset was observed, but it remained within the acceptable range and was smaller than the minimum solder-ball spacing.
The X-ray inspection confirmed that the soldering results were acceptable.
Cross-Section Analysis
For the WLCSP samples, the post-reflow stand-off height was approximately 175 μm, and the solder-ball diameter was approximately 306 μm. Before reflow, the solder-ball height was 195 μm and the diameter was 268 μm. After reflow, the solder ball continued to collapse, resulting in an overall joint height lower than the original solder-ball diameter.
For the FCQFN samples, the post-reflow stand-off height was approximately 67 μm, and the solder diameter was approximately 253 μm. Before reflow, the solder height was approximately 0–50 μm and the solder diameter was approximately 250 μm. After reflow, the terminal was lifted by the solder joint, producing an overall height greater than the original solder height.
Although the two packages produced different stand-off heights and joint profiles, the cross-section results confirmed acceptable soldering for both package types.
Package Reliability Verification: TST300 and TCT1000
TST300 Thermal Shock Test
Eighty FCQFN devices and 80 WLCSP devices were subjected to thermal shock testing between -45 °C and 125 °C. The test evaluated the ability of the assembled devices to withstand thermally induced mechanical stress. After 300 cycles, functional testing was performed, and all tested devices passed.
TCT1000 Temperature Cycle Test
A separate group of 80 FCQFN devices and 80 WLCSP devices underwent temperature cycling between -45 °C and 125 °C. After 1,000 cycles, functional testing was completed, and the test results passed for both package types.
Post-Reliability Cross-Section Verification
WLCSP and FCQFN samples that completed the 300-cycle thermal shock test were cross-sectioned to examine the solder joints after reliability exposure. The cross-section images showed no significant change in the solder-joint condition after testing.
Conclusion
In this evaluation, FCQFN devices were assembled using exactly the same PCB pad and stencil design as the WLCSP devices. X-ray inspection, metallographic cross-section analysis, thermal shock testing, and temperature cycling all confirmed acceptable assembly and reliability performance under the specified conditions.
The results demonstrate that the selected FCQFN and WLCSP packages can share a compatible PCB footprint and stencil design for this application. The approach provides practical support for using different package structures without changing the PCB layout or fabricating a new board. More broadly, compatible pad design can improve design flexibility, help manage package or component substitution, support supply-chain resilience, accelerate product revisions, and reduce redesign cost. Its implementation still requires a careful balance between footprint flexibility, manufacturing capability, solder-joint reliability, and cost.
