Quad Flat No-Lead (QFN) packages are widely adopted and the SMT processes for leadless packages are mature. However, QFNs with a large central exposed pad (E-Pad) are less common in some products, and their thermal-via design and soldering processes are not always analyzed in depth. This article summarizes practical design guidance for the exposed pad and thermal vias, along with stencil aperture strategies, and presents a soldering trial that verified improved assembly yield.
Keywords: QFN, exposed pad (E-Pad), thermal via, stencil design, reflow soldering, voiding, IPC-7093, IPC-4761.
1. QFN Overview
A QFN device is a leadless package featuring a large exposed pad at the center of its bottom surface for heat conduction. Electrical pads are arranged around the periphery. The E-Pad is typically soldered directly to the PCB, and thermal vias under or near the E-Pad help conduct heat into internal or bottom copper planes (often ground), where it is dissipated. The dimensions of the E-Pad, the size and pitch of thermal vias, and the stencil aperture design have a critical impact on both solderability and thermal performance. The design must balance heat dissipation with robust solder joints to maintain product reliability.
Figure 1 | QFN package
2. Ground Pad (Exposed Pad) Design
2.1 E-Pad Land Pattern Requirements
To efficiently transfer heat from the device into the PCB, the PCB land pattern should correspond to the device's E-Pad size, and the exposed pad must achieve a sound solder bond to the board. In general, the PCB land area should be no smaller than the device E-Pad, while maintaining sufficient clearance to prevent bridging with the peripheral pins. A minimum clearance of 0.2 mm is recommended. Figure 2 shows a reference land pattern for the E-Pad.
Figure 2 | E-Pad land pattern reference
2.2 E-Pad Thermal Via Design
Thermal vias effectively conduct heat from the top copper (beneath the E-Pad) to internal or bottom copper planes. The number, diameter, and arrangement of thermal vias significantly affect both thermal performance and SMT assembly outcomes. The required via count depends on the chip's dissipation (power) and the system-level cooling strategy. A typical starting point is a thermal via pitch of about 1.2 mm and via diameter of about 0.3 mm. Figure 3 illustrates an exposed pad and thermal via layout example.
Figure 3 | Exposed pad size and thermal via design
Thermal vias are necessary to conduct heat from the exposed pad to the ground plane. Their number and size depend on package application, device power, and any electrical-performance constraints. Thermal performance generally improves as via count increases, subject to diminishing returns and assembly constraints.
Four common approaches are used to control solder and gas flow through thermal vias under E-Pads: apply solder mask over the via from the top or bottom using dry film; fill from the bottom using liquid photoimageable (LPI) solder mask; or leave the via open (through-via). See Figure 4.
Figure 4 | Solder mask and fill options for thermal vias under an exposed pad
Each method has trade-offs. Top-side solder mask over the via is effective at mitigating voiding but can hinder solder paste printing on the pad. Bottom-side solder mask or bottom fill may allow trapped gases to form large voids, reducing thermal performance. Leaving through-vias open permits solder to wick into the via, which can reduce void size but also reduces the solder volume remaining on the pad. Selection should be based on device power, assembly process capability, and cost; in many cases, a masked-via strategy is preferred. Note: IPC-4761 defines seven methods for via plugging and capping.
3. Stencil Design for the QFN Ground Pad
Stencil thickness and aperture design for the E-Pad are critical to soldering quality. Excess solder can cause solder beads and component float; insufficient solder reduces the contact area and degrades thermal performance. The E-Pad stencil strategy must therefore deliver the proper solder volume and distribute it to minimize voiding.
3.1 Stencil Aperture Pattern
For E-Pads, segment the stencil opening into multiple smaller apertures. The number and size of apertures depend on the E-Pad dimensions, target solder coverage, and spacing to nearby pins. If the E-Pad area exceeds about 4 mm2, segmenting the stencil is recommended (Figure 5) to avoid excessive solder volume that can lift the component during reflow. For QFNs, a solder coverage of about 50%–60% on the E-Pad is commonly targeted (reference IPC-7093).
Figure 5 | Segmented stencil apertures for a QFN E-Pad
3.2 Reducing Solder Loss into Thermal Vias
During reflow, solder paste on the E-Pad can wick into thermal vias, depleting solder from the pad. This is a common SMT issue that can lead to voiding and degraded thermal performance. On double-sided assemblies, solder loss into vias can also affect paste printing on the opposite side (Figure 6).
Figure 6 | Solder loss into thermal vias on the E-Pad
Two approaches are commonly used to mitigate solder loss. One is to apply solder mask on the bottom side over the thermal vias or to use via plugging during PCB fabrication. However, bottom-side mask can trap gas and promote voiding, and via plugging increases PCB cost. The second approach is to move thermal vias outside the E-Pad (Figure 7) or to adjust stencil apertures to avoid via locations under the E-Pad (Figure 8). If vias are moved, re-evaluate the thermal path to confirm adequate heat spreading.
Figure 7 | Place thermal vias outside the E-Pad
Figure 8 | Keep stencil apertures clear of thermal vias
4. Soldering Trial on a QFN Ground Pad
4.1 Background: Poor-Design Case
In one project, a wireless module using an MT7662U QFN had a 9 × 9 mm body and a 7.2 × 7.2 mm exposed pad. The module was soldered to the main board using castellated pads in a secondary reflow step. In a pilot build of 80 units, three units failed detection. Inspection showed the main QFN shifted post-assembly (Figure 9).
Figure 9 | Module QFN device and misalignment defect
4.2 Root Cause Analysis
The initial suspicion was placement shift prior to reflow. A second lot of 50 units was built, verifying module placement before reflow. After secondary reflow and X-ray inspection, one unit still exhibited chip shift, indicating the defect occurred during the second reflow.
Reflow profiling was checked: conveyor speed, airflow, and temperature settings met process requirements. No abnormality was found.
Given the large central ground pad and the module's secondary reflow, the thermal via layout and stencil pattern were suspected. Residual gases within vias can form voids during the second reflow; large voids can produce buoyant forces that lift the package and cause shift.
- Layout review: to meet thermal goals, a dense, fully populated via matrix was placed under the E-Pad. No solder contact area was reserved between vias.
- Stencil review: the stencil used a round-hole matrix that did not avoid thermal vias (Figure 10).
Figure 10 | Original layout and stencil aperture scheme for the module center pad
X-ray inspection revealed large voids in the center pad area, consistent with trapped gas (Figure 11).
Figure 11 | X-ray of module center pad showing large voids
Conclusion: because the stencil apertures did not avoid the thermal vias, residual gas during the second reflow created voids and lifting forces, causing package shift.
4.3 Corrective Actions and Validation
- Layout change: rearranged thermal vias into linear rows, leaving continuous solderable regions for stencil apertures.
- Stencil change: modified apertures to avoid thermal vias, preventing paste from directly covering via holes and providing paths for gas to escape (Figure 12).
Figure 12 | Revised layout and stencil apertures with via keep-out
Post-rework X-ray inspection (Figure 13) showed uniform solder distribution, apertures clear of via locations, and no large voids, eliminating the risk of trapped gas during the second reflow.
Figure 13 | X-ray after redesign showing uniform solder and minimal voiding
4.4 Results
A subsequent validation build of 100 units with the revised layout and stencil experienced no package shift during secondary reflow.
5. Summary
Robust E-Pad soldering demands coordinated design of the pad geometry, solder mask strategy for thermal vias, and stencil apertures. The exposed pad's size, the presence and distribution of thermal vias, and whether vias are masked or open all affect solder flow and voiding as well as thermal performance. Stencil thickness and segmented aperture design determine solder volume and distribution. When the exposed pad also serves as an electrical ground, only a well-optimized design will deliver both reliable electrical contact and effective heat spreading.
5.1 QFNs With Low or No Special Thermal Requirements
For devices with modest thermal needs, the center pad can use small laser-drilled microvias arranged in a uniform array, with keep-outs only for any underlying traces (Figure 14).
Figure 14 | Laser microvias on the center pad
A diagonal stripe stencil pattern is effective. Reduce the pad by 0.1 mm per side, and use 45° diagonal stripes with 0.25 mm stripe width and 0.25 mm spacing. Green indicates the pad and red the stencil apertures in Figure 16.
Figure 15 | Stencil design with 45° diagonal stripes for the center pad
5.2 QFNs With Higher Thermal Requirements (Thermal Via Design Required)
5.2.1 Place thermal vias outside the E-Pad whenever possible, and use diagonal stripe apertures for the E-Pad stencil.
5.2.2 If thermal vias must be placed within the E-Pad, distribute them uniformly but reserve solder-contact areas that allow residual gases in vias to escape during reflow (Figure 16).
Figure 16 | Thermal via distribution on the center pad
Segment the stencil into multiple small apertures and maintain approximately 0.15 mm clearance between apertures and via openings. This prevents solder from covering the via holes, preserves venting paths for gases, and increases the solder-to-copper contact area, improving thermal conduction. See Figure 17.
Figure 17 | Stencil aperture array avoiding thermal vias on the center pad
The thermal pad and stencil strategies described here have been incorporated into internal SMT process and stencil design guidelines, and ongoing builds will continue to monitor and validate soldering performance.
